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From: <sv...@va...> - 2016-10-17 16:17:05
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Author: sewardj
Date: Mon Oct 17 17:16:57 2016
New Revision: 3264
Log:
Merge, from trunk:
3257 Relax the overly-restrictive implementation of (T3) SUB{S}.W Rd,
SP, Rm, {shift}. #354274
Modified:
branches/VEX_3_12_BRANCH/ (props changed)
branches/VEX_3_12_BRANCH/priv/guest_arm_toIR.c
Modified: branches/VEX_3_12_BRANCH/priv/guest_arm_toIR.c
==============================================================================
--- branches/VEX_3_12_BRANCH/priv/guest_arm_toIR.c (original)
+++ branches/VEX_3_12_BRANCH/priv/guest_arm_toIR.c Mon Oct 17 17:16:57 2016
@@ -20576,10 +20576,10 @@
&& rD != 15 && rN == 13 && imm5 <= 31 && how == 0) {
valid = True;
}
- /* also allow "sub.w reg, sp, reg w/ no shift
+ /* also allow "sub.w reg, sp, reg lsl #N for N=0,1,2 or 3
(T1) "SUB (SP minus register) */
if (!valid && INSN0(8,5) == BITS4(1,1,0,1) // sub
- && rD != 15 && rN == 13 && imm5 == 0 && how == 0) {
+ && rD != 15 && rN == 13 && imm5 <= 3 && how == 0) {
valid = True;
}
if (valid) {
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