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From: <sv...@va...> - 2016-10-12 15:02:17
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Author: petarj
Date: Wed Oct 12 16:02:10 2016
New Revision: 3261
Log:
mips: allow VEX to be compiled for soft-float
Force "hardfloat" mode for inline assembly that uses FPU instructions,
but pop original mode at the end of the assembly.
This should allow Valgrind to be compiled as a soft-float binary, but
that executable should be used for soft-float systems only.
Related issue - BZ#351282.
Patch by Aleksandar Rikalo.
Modified:
trunk/priv/guest_mips_helpers.c
Modified: trunk/priv/guest_mips_helpers.c
==============================================================================
--- trunk/priv/guest_mips_helpers.c (original)
+++ trunk/priv/guest_mips_helpers.c Wed Oct 12 16:02:10 2016
@@ -459,75 +459,93 @@
#endif
#define ASM_VOLATILE_UNARY32(inst) \
- __asm__ volatile("cfc1 $t0, $31" "\n\t" \
+ __asm__ volatile(".set push" "\n\t" \
+ ".set hardfloat" "\n\t" \
+ "cfc1 $t0, $31" "\n\t" \
"ctc1 %2, $31" "\n\t" \
"mtc1 %1, $f20" "\n\t" \
#inst" $f20, $f20" "\n\t" \
"cfc1 %0, $31" "\n\t" \
"ctc1 $t0, $31" "\n\t" \
+ ".set pop" "\n\t" \
: "=r" (ret) \
: "r" (loFsVal), "r" (fcsr) \
: "t0", "$f20" \
);
#define ASM_VOLATILE_UNARY32_DOUBLE(inst) \
- __asm__ volatile("cfc1 $t0, $31" "\n\t" \
+ __asm__ volatile(".set push" "\n\t" \
+ ".set hardfloat" "\n\t" \
+ "cfc1 $t0, $31" "\n\t" \
"ctc1 %2, $31" "\n\t" \
"ldc1 $f20, 0(%1)" "\n\t" \
#inst" $f20, $f20" "\n\t" \
"cfc1 %0, $31" "\n\t" \
"ctc1 $t0, $31" "\n\t" \
+ ".set pop" "\n\t" \
: "=r" (ret) \
: "r" (&fsVal), "r" (fcsr) \
: "t0", "$f20", "$f21" \
);
#define ASM_VOLATILE_UNARY64(inst) \
- __asm__ volatile("cfc1 $t0, $31" "\n\t" \
+ __asm__ volatile(".set push" "\n\t" \
+ ".set hardfloat" "\n\t" \
+ "cfc1 $t0, $31" "\n\t" \
"ctc1 %2, $31" "\n\t" \
"ldc1 $f24, 0(%1)" "\n\t" \
#inst" $f24, $f24" "\n\t" \
"cfc1 %0, $31" "\n\t" \
"ctc1 $t0, $31" "\n\t" \
+ ".set pop" "\n\t" \
: "=r" (ret) \
: "r" (&(addr[fs])), "r" (fcsr) \
: "t0", "$f24" \
);
#define ASM_VOLATILE_BINARY32(inst) \
- __asm__ volatile("cfc1 $t0, $31" "\n\t" \
+ __asm__ volatile(".set push" "\n\t" \
+ ".set hardfloat" "\n\t" \
+ "cfc1 $t0, $31" "\n\t" \
"ctc1 %3, $31" "\n\t" \
"mtc1 %1, $f20" "\n\t" \
"mtc1 %2, $f22" "\n\t" \
#inst" $f20, $f20, $f22" "\n\t" \
"cfc1 %0, $31" "\n\t" \
"ctc1 $t0, $31" "\n\t" \
+ ".set pop" "\n\t" \
: "=r" (ret) \
: "r" (loFsVal), "r" (loFtVal), "r" (fcsr) \
: "t0", "$f20", "$f22" \
);
#define ASM_VOLATILE_BINARY32_DOUBLE(inst) \
- __asm__ volatile("cfc1 $t0, $31" "\n\t" \
+ __asm__ volatile(".set push" "\n\t" \
+ ".set hardfloat" "\n\t" \
+ "cfc1 $t0, $31" "\n\t" \
"ctc1 %3, $31" "\n\t" \
"ldc1 $f20, 0(%1)" "\n\t" \
"ldc1 $f22, 0(%2)" "\n\t" \
#inst" $f20, $f20, $f22" "\n\t" \
"cfc1 %0, $31" "\n\t" \
"ctc1 $t0, $31" "\n\t" \
+ ".set pop" "\n\t" \
: "=r" (ret) \
: "r" (&fsVal), "r" (&ftVal), "r" (fcsr) \
: "t0", "$f20", "$f21", "$f22", "$f23" \
);
#define ASM_VOLATILE_BINARY64(inst) \
- __asm__ volatile("cfc1 $t0, $31" "\n\t" \
+ __asm__ volatile(".set push" "\n\t" \
+ ".set hardfloat" "\n\t" \
+ "cfc1 $t0, $31" "\n\t" \
"ctc1 %3, $31" "\n\t" \
"ldc1 $f24, 0(%1)" "\n\t" \
"ldc1 $f26, 0(%2)" "\n\t" \
#inst" $f24, $f24, $f26" "\n\t" \
"cfc1 %0, $31" "\n\t" \
"ctc1 $t0, $31" "\n\t" \
+ ".set pop" "\n\t" \
: "=r" (ret) \
: "r" (&(addr[fs])), "r" (&(addr[ft])), "r" (fcsr) \
: "t0", "$f24", "$f26" \
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