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From: Carl E. L. <ce...@us...> - 2016-02-24 23:59:58
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I noticed that the power none/tests/ppc64/test_isa_2_07.c test is
generating some warnings from Valgrind. I have fixed a number of issues
with the test stepping off the end of the various data arrays. I have
one issue left with the BCD add and subtract instructions. I get the
message:
==28469== Use of uninitialised value of size 8
==28469== at 0x41D8BD8: _itoa_word (_itoa.c:180)
==28469== by 0x41DB05B: vfprintf@@GLIBC_2.17 (vfprintf.c:1641)
==28469== by 0x10001F83: test_av_bcd (test_isa_2_07_part1.c:1426)
==28469== by 0x1000432B: do_tests (test_isa_2_07_part1.c:2020)
==28469== by 0x1000432B: main (test_isa_2_07_part1.c:2132)
==28469==
==28469== Conditional jump or move depends on uninitialised value(s)
==28469== at 0x41DB0C8: vfprintf@@GLIBC_2.17 (vfprintf.c:1641)
==28469== by 0x41E352F: printf@@GLIBC_2.17 (printf.c:33)
==28469== by 0x10001F83: test_av_bcd (test_isa_2_07_part1.c:1426)
==28469== by 0x1000432B: do_tests (test_isa_2_07_part1.c:2020)
==28469== by 0x1000432B: main (test_isa_2_07_part1.c:2132)
==28469==
when the result of the BCD add or subtract instruction is printed.
The printing of the two source values is fine. The test case has some
similar instructions that also use V128 which are structured identically
and work fine. I can't find any issues with the test case using any
uninitialized data.
The BCD add instruction maps to Iop_BCDAdd. The instruction takes two
128 bit BCD numbers and generates a 128 bit BCD result. There is an
additional I8 field (ps) which indicates if the instruction should set
the condition code values or not. The Iop definition is as follows:
VEX/priv/ir_defs.c
case Iop_BCDAdd:
case Iop_BCDSub:
TERNARY(Ity_V128,Ity_V128, Ity_I8, Ity_V128);
In memcheck/mc_translate.c we have:
/* BCDIops */
case Iop_BCDAdd:
case Iop_BCDSub:
complainIfUndefined(mce, atom3, NULL);
return assignNew('V', mce, Ity_V128, triop(op, vatom1, vatom2, atom3));
The BCD add and subtract instructions are mapped to Iop_BCDAdd and Iop_BCDSub in
VEX/priv/guest_ppc_toIR.c:
switch (opc2) {
case 0x1: // bcdadd
DIP("bcdadd. v%d,v%d,v%d,%u\n", vRT_addr, vRA_addr, vRB_addr, ps);
assign( dst, triop( Iop_BCDAdd, mkexpr( vA ),
mkexpr( vB ), mkU8( ps ) ) );
putVReg( vRT_addr, mkexpr(dst));
return True;
case 0x41: // bcdsub
DIP("bcdsub. v%d,v%d,v%d,%u\n", vRT_addr, vRA_addr, vRB_addr, ps);
assign( dst, triop( Iop_BCDSub, mkexpr( vA ),
mkexpr( vB ), mkU8( ps ) ) );
putVReg( vRT_addr, mkexpr(dst));
return True;
The register use of the destination is set to HRmWrite, the two sources are HRmRead
the ps value use is Pri_Imm.
I have tried running the test case using gdb. I have stepped through the assembly code
where the BCD add instruction gets executed and printed the source and destination
register values as well as the shadow registers. The source shadow register values
are all zeros indicating all the bits are valid. Similarly, the shadow bits for the
result are all zeros. I have been looking for any Valgrind debug flags that might help
to debug the issue with the shadow bits. If anyone has any suggestions on debugging
the issue or sees an error in code I would appreciate the help.
Thanks.
Carl Love
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