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From: <sv...@va...> - 2015-11-26 18:17:42
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Author: petarj
Date: Thu Nov 26 18:17:33 2015
New Revision: 3205
Log:
mips: add definitions of expected ISA levels
Add values of supported isa level for MIPS CPU models. This extended
information will be packed in 31:24 bits in hwcaps.
Modified:
trunk/priv/guest_mips_toIR.c
trunk/priv/host_mips_isel.c
trunk/priv/main_main.c
trunk/pub/libvex.h
Modified: trunk/priv/guest_mips_toIR.c
==============================================================================
--- trunk/priv/guest_mips_toIR.c (original)
+++ trunk/priv/guest_mips_toIR.c Thu Nov 26 18:17:33 2015
@@ -17290,7 +17290,7 @@
mode64 = guest_arch != VexArchMIPS32;
#if (__mips_fpr==64)
- fp_mode64 = ((VEX_MIPS_REV(archinfo->hwcaps) == VEX_PRID_CPU_32FPR)
+ fp_mode64 = (VEX_MIPS_HAS_32_64BIT_FPRS(archinfo->hwcaps)
|| guest_arch == VexArchMIPS64);
#endif
Modified: trunk/priv/host_mips_isel.c
==============================================================================
--- trunk/priv/host_mips_isel.c (original)
+++ trunk/priv/host_mips_isel.c Thu Nov 26 18:17:33 2015
@@ -4184,7 +4184,7 @@
mode64 = arch_host != VexArchMIPS32;
#if (__mips_fpr==64)
- fp_mode64 = ((VEX_MIPS_REV(hwcaps_host) == VEX_PRID_CPU_32FPR)
+ fp_mode64 = (VEX_MIPS_HAS_32_64BIT_FPRS(hwcaps_host)
|| arch_host == VexArchMIPS64);
#endif
Modified: trunk/priv/main_main.c
==============================================================================
--- trunk/priv/main_main.c (original)
+++ trunk/priv/main_main.c Thu Nov 26 18:17:33 2015
@@ -1738,7 +1738,12 @@
return "Loongson-baseline";
}
- return "mips64-baseline";
+ /* MIPS64 baseline. */
+ if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_MIPS) {
+ return "mips64-baseline";
+ }
+
+ return "Unsupported baseline";
}
static const HChar* show_hwcaps_tilegx ( UInt hwcaps )
Modified: trunk/pub/libvex.h
==============================================================================
--- trunk/pub/libvex.h (original)
+++ trunk/pub/libvex.h Thu Nov 26 18:17:33 2015
@@ -222,15 +222,32 @@
#define VEX_PRID_IMP_34K 0x9500
#define VEX_PRID_IMP_74K 0x9700
+/*
+ * Instead of Company Options values, bits 31:24 will be packed with
+ * additional information, such as isa level and presence of FPU unit
+ * with 32 64-bit registers.
+ */
+#define VEX_MIPS_CPU_ISA_M32R1 0x01000000
+#define VEX_MIPS_CPU_ISA_M32R2 0x02000000
+#define VEX_MIPS_CPU_ISA_M64R1 0x04000000
+#define VEX_MIPS_CPU_ISA_M64R2 0x08000000
+#define VEX_MIPS_CPU_ISA_M32R6 0x10000000
+#define VEX_MIPS_CPU_ISA_M64R6 0x20000000
/* CPU has FPU and 32 dbl. prec. FP registers */
-#define VEX_PRID_CPU_32FPR 0x00000040
-
+#define VEX_MIPS_CPU_32FPR 0x40000000
+/* Get MIPS Extended Information */
+#define VEX_MIPS_EX_INFO(x) ((x) & 0xFF000000)
/* Get MIPS Company ID from HWCAPS */
#define VEX_MIPS_COMP_ID(x) ((x) & 0x00FF0000)
/* Get MIPS Processor ID from HWCAPS */
#define VEX_MIPS_PROC_ID(x) ((x) & 0x0000FF00)
/* Get MIPS Revision from HWCAPS */
#define VEX_MIPS_REV(x) ((x) & 0x000000FF)
+/* Check if the processor has 32 64-bit FP registers */
+#define VEX_MIPS_HAS_32_64BIT_FPRS(x) (VEX_MIPS_EX_INFO(x) | VEX_MIPS_CPU_32FPR)
+/* Check if the processor supports MIPS32R2. */
+#define VEX_MIPS_CPU_HAS_MIPS32R2(x) (VEX_MIPS_EX_INFO(x) | \
+ VEX_MIPS_CPU_ISA_M32R2)
/* Check if the processor supports DSP ASE Rev 2. */
#define VEX_MIPS_PROC_DSP2(x) ((VEX_MIPS_COMP_ID(x) == VEX_PRID_COMP_MIPS) && \
(VEX_MIPS_PROC_ID(x) == VEX_PRID_IMP_74K))
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