Re: [Valgrind-users] Cachegrind - Tracing LLC misses

[Josef W. <Jos...@gm...>]

Am 25.09.2015 um 22:27 schrieb martin:
> I'm trying to do a memory trace of my application, but only for  
> operations that go to DRAM, that is, only if there was a LLC miss  
> should I care. Is it possible to achieve that with Cachegrind? AFAICS,  
> it only counts the number of events (and where they happened), but  
> maybe it wouldn't be too hard to modify it to print the address every  
> time a LLC miss happens. If anyone could point me to the right place  
> to look, I would appreciate it.

See cachegrind/cg_sim.c, function "cachesim_D1_doref". The "*(mL)++" is
incrementing the counter for a last-level cache miss. At this point,
you can use VG_(printf) to print out the address ("a").
If you also want to print out the address of the instruction doing the
memory
access, or whether it is a read or write, you need to modify the callers
of cachesim_D1_doref (and change the return value to tell if it's a LLC
miss).

Josef

> 
> Thank you,
> Martin
> 
> 
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