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From: <sv...@va...> - 2015-07-21 22:27:26
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Author: petarj
Date: Tue Jul 21 23:27:19 2015
New Revision: 3166
Log:
mips64: make cavium CvmCount register accessible via rdhwr
Fixes reported issue BZ #346031.
Patch by Crestez Dan Leonard.
Modified:
trunk/priv/guest_mips_helpers.c
trunk/priv/guest_mips_toIR.c
Modified: trunk/priv/guest_mips_helpers.c
==============================================================================
--- trunk/priv/guest_mips_helpers.c (original)
+++ trunk/priv/guest_mips_helpers.c Tue Jul 21 23:27:19 2015
@@ -1085,6 +1085,10 @@
__asm__ __volatile__("rdhwr %0, $1\n\t" : "=r" (x) );
break;
+ case 31: /* x = CVMX_get_cycles() */
+ __asm__ __volatile__("rdhwr %0, $31\n\t" : "=r" (x) );
+ break;
+
default:
vassert(0);
break;
@@ -1100,6 +1104,10 @@
__asm__ __volatile__("rdhwr %0, $1\n\t" : "=r" (x) );
break;
+ case 31: /* x = CVMX_get_cycles() */
+ __asm__ __volatile__("rdhwr %0, $31\n\t" : "=r" (x) );
+ break;
+
default:
vassert(0);
break;
Modified: trunk/priv/guest_mips_toIR.c
==============================================================================
--- trunk/priv/guest_mips_toIR.c (original)
+++ trunk/priv/guest_mips_toIR.c Tue Jul 21 23:27:19 2015
@@ -15121,7 +15121,10 @@
if (rd == 29) {
putIReg(rt, getULR());
#if defined(__mips__) && ((defined(__mips_isa_rev) && __mips_isa_rev >= 2))
- } else if (rd == 1) {
+ } else if (rd == 1
+ || (rd == 31
+ && VEX_MIPS_COMP_ID(archinfo->hwcaps)
+ == VEX_PRID_COMP_CAVIUM)) {
if (mode64) {
IRTemp val = newTemp(Ity_I64);
IRExpr** args = mkIRExprVec_2 (mkU64(rt), mkU64(rd));
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