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From: <sv...@va...> - 2015-04-22 16:15:48
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Author: carll
Date: Wed Apr 22 17:15:41 2015
New Revision: 3143
Log:
Add support for the TEXASRU register. This register contains information on
transactional memory instruction summary information. This register contains
the upper 32-bits of the transaction information. Note, the valgrind
implementation of transactional memory instructions is limited. Currently, the
contents of the TEXASRU register will always return 0. The lower 64-bits of
the trasnaction information in the TEXASR register will contain the failure
information as setup by Valgrind.
This commit contains the changes needed to support the TEXASRU register on
PPC64.
This support requires changing the value of MAX_REG_WRITE_SIZE in
memcheck/mc_main.c from 1696 to 1712. The change is made in the corresponding
valgrind commit.
This patch addresses Bugzilla 346474
Modified:
trunk/priv/guest_ppc_toIR.c
trunk/pub/libvex_guest_ppc32.h
trunk/pub/libvex_guest_ppc64.h
Modified: trunk/priv/guest_ppc_toIR.c
==============================================================================
--- trunk/priv/guest_ppc_toIR.c (original)
+++ trunk/priv/guest_ppc_toIR.c Wed Apr 22 17:15:41 2015
@@ -286,6 +286,7 @@
#define OFFB_NRADDR_GPR2 offsetofPPCGuestState(guest_NRADDR_GPR2)
#define OFFB_TFHAR offsetofPPCGuestState(guest_TFHAR)
#define OFFB_TEXASR offsetofPPCGuestState(guest_TEXASR)
+#define OFFB_TEXASRU offsetofPPCGuestState(guest_TEXASRU)
#define OFFB_TFIAR offsetofPPCGuestState(guest_TFIAR)
@@ -436,6 +437,7 @@
PPC_GST_TFHAR, // Transactional Failure Handler Address Register
PPC_GST_TFIAR, // Transactional Failure Instruction Address Register
PPC_GST_TEXASR, // Transactional EXception And Summary Register
+ PPC_GST_TEXASRU, // Transactional EXception And Summary Register Upper
PPC_GST_MAX
} PPC_GST;
@@ -2739,6 +2741,9 @@
case PPC_GST_TEXASR:
return IRExpr_Get( OFFB_TEXASR, ty );
+ case PPC_GST_TEXASRU:
+ return IRExpr_Get( OFFB_TEXASRU, ty );
+
case PPC_GST_TFIAR:
return IRExpr_Get( OFFB_TFIAR, ty );
@@ -2907,6 +2912,12 @@
vassert( ty_src == Ity_I64 );
stmt( IRStmt_Put( OFFB_TEXASR, src ) );
break;
+
+ case PPC_GST_TEXASRU:
+ vassert( ty_src == Ity_I32 );
+ stmt( IRStmt_Put( OFFB_TEXASRU, src ) );
+ break;
+
case PPC_GST_TFIAR:
vassert( ty_src == Ity_I64 );
stmt( IRStmt_Put( OFFB_TFIAR, src ) );
@@ -3337,9 +3348,10 @@
static void storeTMfailure( Addr64 err_address, ULong tm_reason,
Addr64 handler_address )
{
- putGST( PPC_GST_TFIAR, mkU64( err_address ) );
- putGST( PPC_GST_TEXASR, mkU64( tm_reason ) );
- putGST( PPC_GST_TFHAR, mkU64( handler_address ) );
+ putGST( PPC_GST_TFIAR, mkU64( err_address ) );
+ putGST( PPC_GST_TEXASR, mkU64( tm_reason ) );
+ putGST( PPC_GST_TEXASRU, mkU32( 0 ) );
+ putGST( PPC_GST_TFHAR, mkU64( handler_address ) );
}
/*------------------------------------------------------------*/
@@ -7115,6 +7127,10 @@
DIP("mfspr r%u (TEXASR)\n", rD_addr);
putIReg( rD_addr, getGST( PPC_GST_TEXASR) );
break;
+ case 0x83: // 131
+ DIP("mfspr r%u (TEXASRU)\n", rD_addr);
+ putIReg( rD_addr, getGST( PPC_GST_TEXASRU) );
+ break;
case 0x100:
DIP("mfvrsave r%u\n", rD_addr);
putIReg( rD_addr, mkWidenFrom32(ty, getGST( PPC_GST_VRSAVE ),
Modified: trunk/pub/libvex_guest_ppc32.h
==============================================================================
--- trunk/pub/libvex_guest_ppc32.h (original)
+++ trunk/pub/libvex_guest_ppc32.h Wed Apr 22 17:15:41 2015
@@ -241,9 +241,10 @@
/* 1360 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register
/* 1368 */ ULong guest_TEXASR; // Transaction EXception And Summary Register
/* 1376 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register
+ /* 1384 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
/* Padding to make it have an 16-aligned size */
- /* 1384 */ UInt padding2;
+ /* 1388 */ UInt padding2;
}
VexGuestPPC32State;
Modified: trunk/pub/libvex_guest_ppc64.h
==============================================================================
--- trunk/pub/libvex_guest_ppc64.h (original)
+++ trunk/pub/libvex_guest_ppc64.h Wed Apr 22 17:15:41 2015
@@ -282,6 +282,12 @@
/* 1656 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register
/* 1664 */ ULong guest_TEXASR; // Transaction EXception And Summary Register
/* 1672 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register
+ /* 1680 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
+
+ /* Padding to make it have an 16-aligned size */
+ /* 1684 */ UInt padding1;
+ /* 1688 */ UInt padding2;
+ /* 1692 */ UInt padding3;
}
VexGuestPPC64State;
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