|
From: Carl E. L. <ce...@us...> - 2015-04-21 18:29:10
|
Julian: I received a request to add support for the PPC64 TEXASRU register, (https://bugzilla.linux.ibm.com/show_bug.cgi?id=124179). It is one of the registers used to hold information on the transactional memory instructions. I found that I need to increase the #define value of MAX_REG_WRITE_SIZE from 1696 to 1712. The value must be as large as the the biggest guest state. The value 1712 is the minimum value that is required with the new PPC64 TEXASRU register to meet the requirement. Since I am outside of the PPC code space, I am asking for permission to make this change. The full patch is given below for your review. Carl Love ----------------------------------------------------------------------- PPC64, add support for the TEXASRU register. The TEXASRU register is a 32-bit register that holds the upper 32 bits of the Transaction EXception And Summary Register (TEXASR). --- VEX/priv/guest_ppc_toIR.c | 22 +++++++++++++++++++--- VEX/pub/libvex_guest_ppc32.h | 3 ++- VEX/pub/libvex_guest_ppc64.h | 6 ++++++ memcheck/mc_main.c | 2 +- 4 files changed, 28 insertions(+), 5 deletions(-) diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 6a29c47..b1326da 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -286,6 +286,7 @@ static void* fnptr_to_fnentry( const VexAbiInfo* vbi, void* f ) #define OFFB_NRADDR_GPR2 offsetofPPCGuestState(guest_NRADDR_GPR2) #define OFFB_TFHAR offsetofPPCGuestState(guest_TFHAR) #define OFFB_TEXASR offsetofPPCGuestState(guest_TEXASR) +#define OFFB_TEXASRU offsetofPPCGuestState(guest_TEXASRU) #define OFFB_TFIAR offsetofPPCGuestState(guest_TFIAR) @@ -436,6 +437,7 @@ typedef enum { PPC_GST_TFHAR, // Transactional Failure Handler Address Register PPC_GST_TFIAR, // Transactional Failure Instruction Address Register PPC_GST_TEXASR, // Transactional EXception And Summary Register + PPC_GST_TEXASRU, // Transactional EXception And Summary Register Upper PPC_GST_MAX } PPC_GST; @@ -2739,6 +2741,9 @@ static IRExpr* /* :: Ity_I32/64 */ getGST ( PPC_GST reg ) case PPC_GST_TEXASR: return IRExpr_Get( OFFB_TEXASR, ty ); + case PPC_GST_TEXASRU: + return IRExpr_Get( OFFB_TEXASRU, ty ); + case PPC_GST_TFIAR: return IRExpr_Get( OFFB_TFIAR, ty ); @@ -2907,6 +2912,12 @@ static void putGST ( PPC_GST reg, IRExpr* src ) vassert( ty_src == Ity_I64 ); stmt( IRStmt_Put( OFFB_TEXASR, src ) ); break; + + case PPC_GST_TEXASRU: + vassert( ty_src == Ity_I32 ); + stmt( IRStmt_Put( OFFB_TEXASRU, src ) ); + break; + case PPC_GST_TFIAR: vassert( ty_src == Ity_I64 ); stmt( IRStmt_Put( OFFB_TFIAR, src ) ); @@ -3337,9 +3348,10 @@ static ULong generate_TMreason( UInt failure_code, static void storeTMfailure( Addr64 err_address, ULong tm_reason, Addr64 handler_address ) { - putGST( PPC_GST_TFIAR, mkU64( err_address ) ); - putGST( PPC_GST_TEXASR, mkU64( tm_reason ) ); - putGST( PPC_GST_TFHAR, mkU64( handler_address ) ); + putGST( PPC_GST_TFIAR, mkU64( err_address ) ); + putGST( PPC_GST_TEXASR, mkU64( tm_reason ) ); + putGST( PPC_GST_TEXASRU, mkU32( 0 ) ); + putGST( PPC_GST_TFHAR, mkU64( handler_address ) ); } /*------------------------------------------------------------*/ @@ -7115,6 +7127,10 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr ) DIP("mfspr r%u (TEXASR)\n", rD_addr); putIReg( rD_addr, getGST( PPC_GST_TEXASR) ); break; + case 0x83: // 131 + DIP("mfspr r%u (TEXASRU)\n", rD_addr); + putIReg( rD_addr, getGST( PPC_GST_TEXASRU) ); + break; case 0x100: DIP("mfvrsave r%u\n", rD_addr); putIReg( rD_addr, mkWidenFrom32(ty, getGST( PPC_GST_VRSAVE ), diff --git a/VEX/pub/libvex_guest_ppc32.h b/VEX/pub/libvex_guest_ppc32.h index 35dd318..3c2fd9e 100644 --- a/VEX/pub/libvex_guest_ppc32.h +++ b/VEX/pub/libvex_guest_ppc32.h @@ -241,9 +241,10 @@ typedef /* 1360 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register /* 1368 */ ULong guest_TEXASR; // Transaction EXception And Summary Register /* 1376 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register + /* 1384 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper /* Padding to make it have an 16-aligned size */ - /* 1384 */ UInt padding2; + /* 1388 */ UInt padding2; } VexGuestPPC32State; diff --git a/VEX/pub/libvex_guest_ppc64.h b/VEX/pub/libvex_guest_ppc64.h index 9a4caed..13a3540 100644 --- a/VEX/pub/libvex_guest_ppc64.h +++ b/VEX/pub/libvex_guest_ppc64.h @@ -282,6 +282,12 @@ typedef /* 1656 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register /* 1664 */ ULong guest_TEXASR; // Transaction EXception And Summary Register /* 1672 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register + /* 1680 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper + + /* Padding to make it have an 16-aligned size */ + /* 1684 */ UInt padding1; + /* 1688 */ UInt padding2; + /* 1692 */ UInt padding3; } VexGuestPPC64State; diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c index 5cd2414..1fc1561 100644 --- a/memcheck/mc_main.c +++ b/memcheck/mc_main.c @@ -4142,7 +4142,7 @@ static UInt mb_get_origin_for_guest_offset ( ThreadId tid, static void mc_post_reg_write ( CorePart part, ThreadId tid, PtrdiffT offset, SizeT size) { -# define MAX_REG_WRITE_SIZE 1696 +# define MAX_REG_WRITE_SIZE 1712 UChar area[MAX_REG_WRITE_SIZE]; tl_assert(size <= MAX_REG_WRITE_SIZE); VG_(memset)(area, V_BITS8_DEFINED, size); -- 1.8.3.1 |