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From: <sv...@va...> - 2014-11-23 17:22:23
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Author: sewardj
Date: Sun Nov 23 17:22:16 2014
New Revision: 3011
Log:
Merge, from trunk, r2985
335713 arm64: unhanded instruction: prfm (immediate)
2985
Modified:
branches/VEX_3_10_BRANCH/ (props changed)
branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
Modified: branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c
==============================================================================
--- branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c (original)
+++ branches/VEX_3_10_BRANCH/priv/guest_arm64_toIR.c Sun Nov 23 17:22:16 2014
@@ -6358,6 +6358,22 @@
return True;
}
+ /* ------------------ PRFM (immediate) ------------------ */
+ /* 31 21 9 4
+ 11 111 00110 imm12 n t PRFM pfrop=Rt, [Xn|SP, #pimm]
+ */
+ if (INSN(31,22) == BITS10(1,1,1,1,1,0,0,1,1,0)) {
+ UInt imm12 = INSN(21,10);
+ UInt nn = INSN(9,5);
+ UInt tt = INSN(4,0);
+ /* Generating any IR here is pointless, except for documentation
+ purposes, as it will get optimised away later. */
+ IRTemp ea = newTemp(Ity_I64);
+ assign(ea, binop(Iop_Add64, getIReg64orSP(nn), mkU64(imm12 * 8)));
+ DIP("prfm prfop=%u, [%s, #%u]\n", tt, nameIReg64orSP(nn), imm12 * 8);
+ return True;
+ }
+
vex_printf("ARM64 front end: load_store\n");
return False;
# undef INSN
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