|
From: <sv...@va...> - 2014-09-04 11:45:42
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Author: sewardj
Date: Thu Sep 4 11:45:26 2014
New Revision: 14458
Log:
arm64: enable test cases for str bN, [reg, reg etc] and str hN, [reg,
reg etc]. Pertaining to #337762, vex r2943.
Modified:
trunk/none/tests/arm64/memory.c
trunk/none/tests/arm64/memory.stdout.exp
Modified: trunk/none/tests/arm64/memory.c
==============================================================================
--- trunk/none/tests/arm64/memory.c (original)
+++ trunk/none/tests/arm64/memory.c Thu Sep 4 11:45:26 2014
@@ -589,7 +589,6 @@
MEM_TEST("ldr s17, [x5, w6, sxtw]", 12, 4);
MEM_TEST("ldr s17, [x5, w6, sxtw #2]", 12, -4);
-#if 0
MEM_TEST("str h17, [x5, x6]", 12, -4);
MEM_TEST("str h17, [x5, x6, lsl #1]", 12, -4);
MEM_TEST("str h17, [x5, w6, uxtw]", 12, 4);
@@ -615,7 +614,6 @@
MEM_TEST("ldr b17, [x5, w6, uxtw #0]", 12, 4);
MEM_TEST("ldr b17, [x5, w6, sxtw]", 12, 4);
MEM_TEST("ldr b17, [x5, w6, sxtw #0]", 12, -4);
-#endif
////////////////////////////////////////////////////////////////
printf("LDRS{B,H,W} (integer register, SX)\n");
Modified: trunk/none/tests/arm64/memory.stdout.exp
==============================================================================
--- trunk/none/tests/arm64/memory.stdout.exp (original)
+++ trunk/none/tests/arm64/memory.stdout.exp Thu Sep 4 11:45:26 2014
@@ -4007,6 +4007,726 @@
0 x5 (sub, base reg)
0 x6 (sub, index reg)
+str h17, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. d9 84 .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str h17, [x5, x6, lsl #1] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. a9 98 .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str h17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 2c 25 .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str h17, [x5, w6, uxtw #1] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. c3 7f .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str h17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 28 75 .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str h17, [x5, w6, sxtw #1] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. 92 d2 .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr h17, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ d4026e495c0bc705 v17.d[0] (xor, xfer vecreg #1)
+ 095d12c1d2eff385 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr h17, [x5, x6, lsl #1] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 6aa53ab8bb2197e9 v17.d[0] (xor, xfer vecreg #1)
+ b385aca0bf4b9e22 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr h17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 3e6c54815fb41ceb v17.d[0] (xor, xfer vecreg #1)
+ 7e79af58033aa46b v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr h17, [x5, w6, uxtw #1] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 14cc1f374977a711 v17.d[0] (xor, xfer vecreg #1)
+ ae2dfffc22f127b4 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr h17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ b039006f7f1f742b v17.d[0] (xor, xfer vecreg #1)
+ 86947fa19fa34d52 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr h17, [x5, w6, sxtw #1] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ d6275abd045ffef5 v17.d[0] (xor, xfer vecreg #1)
+ 4ca4145bfe843997 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str b17, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. 57 .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str b17, [x5, x6, lsl #0] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. 90 .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str b17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 39 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str b17, [x5, w6, uxtw #0] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 56 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str b17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] c4 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str b17, [x5, w6, sxtw #0] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. 19 .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr b17, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 41d5efcda6de2156 v17.d[0] (xor, xfer vecreg #1)
+ e9813744a9ef2675 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr b17, [x5, x6, lsl #0] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 451b26983632a3b0 v17.d[0] (xor, xfer vecreg #1)
+ a5208074ab9d52cc v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr b17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ b7f65aad3a726561 v17.d[0] (xor, xfer vecreg #1)
+ b2fce36c334d89c0 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr b17, [x5, w6, uxtw #0] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 5bd9f1a0b4530a92 v17.d[0] (xor, xfer vecreg #1)
+ 54074141c636eda4 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr b17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ f53a4c05aa893694 v17.d[0] (xor, xfer vecreg #1)
+ cf378107e789a4cc v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr b17, [x5, w6, sxtw #0] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 498cd26f20c78e01 v17.d[0] (xor, xfer vecreg #1)
+ 667e85d11a7cd18c v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
LDRS{B,H,W} (integer register, SX)
ldrsw x13, [x5,x6] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
@@ -4025,7 +4745,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 4991809b592766de x13 (xor, xfer intreg #1)
+ 45283e5489578bad x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4055,7 +4775,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- ecab746191e71575 x13 (xor, xfer intreg #1)
+ 38a305c49938b487 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4085,7 +4805,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 22a74ae38fee367e x13 (xor, xfer intreg #1)
+ 55d009793f6420d6 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4115,7 +4835,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 1cd6637ce5e8e8da x13 (xor, xfer intreg #1)
+ b01695c953ae6f8a x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4145,7 +4865,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 9eab24c24f0ac55c x13 (xor, xfer intreg #1)
+ 607cc36833167627 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4175,7 +4895,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 6c9cf046e9a2bfa3 x13 (xor, xfer intreg #1)
+ 39eb4f850cc79ba6 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4205,7 +4925,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- b5e3d360b748922c x13 (xor, xfer intreg #1)
+ 42c23127cfc887a0 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4235,7 +4955,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- fb9f3c5f3b2bddc4 x13 (xor, xfer intreg #1)
+ 807c4710d2a76a71 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4265,7 +4985,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- ba667ce49472fbca x13 (xor, xfer intreg #1)
+ 49720b298caae7b8 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4295,7 +5015,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- ea7d6667dd92cdf2 x13 (xor, xfer intreg #1)
+ a7699d0ab48417a3 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4325,7 +5045,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- afc148d693ed6288 x13 (xor, xfer intreg #1)
+ e67b59bc63148b29 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4355,7 +5075,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 58d88efd9452995d x13 (xor, xfer intreg #1)
+ 31ad8decd3c3706e x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4385,7 +5105,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- a8359b70e176717b x13 (xor, xfer intreg #1)
+ 8b4666106a2b3d08 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4415,7 +5135,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 654ed4c3800da87c x13 (xor, xfer intreg #1)
+ 13d6e5cba693fd33 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4445,7 +5165,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 51959d8974ca561f x13 (xor, xfer intreg #1)
+ 2c7554dbfdb54557 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4475,7 +5195,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 32805957c26143f5 x13 (xor, xfer intreg #1)
+ 999716d25bb7ce2f x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4505,7 +5225,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- ca816dc1927863b6 x13 (xor, xfer intreg #1)
+ 1db091457728f8cd x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4535,7 +5255,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- de0e3d5a79ef9f53 x13 (xor, xfer intreg #1)
+ 7d3326c8ac434998 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4565,7 +5285,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- ce66d34814b16659 x13 (xor, xfer intreg #1)
+ 7d963ceef526ab13 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4595,7 +5315,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 89989f6cc65775a1 x13 (xor, xfer intreg #1)
+ e14c354c601b31f6 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4625,7 +5345,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 578206f2f140e49e x13 (xor, xfer intreg #1)
+ 6dc87576994ee1f1 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4655,7 +5375,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 54bd9f2dc8392d13 x13 (xor, xfer intreg #1)
+ e4806100a3735e28 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4685,7 +5405,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- b0320b9e0885afab x13 (xor, xfer intreg #1)
+ 0ce65d7d823f4bb6 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4715,7 +5435,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- a1e0a2c260cad60b x13 (xor, xfer intreg #1)
+ 588f337dc59ab1e9 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4745,7 +5465,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 45283e54c51f5bad x13 (xor, xfer intreg #1)
+ 7a9013a2d09a0a55 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4775,7 +5495,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- c75cfa3b6ceb89d9 x13 (xor, xfer intreg #1)
+ 49bc9573b76ddc40 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4805,7 +5525,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- aa2ff686984d59d6 x13 (xor, xfer intreg #1)
+ d866b8875bffc2ee x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4835,7 +5555,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- b01695c9b1059196 x13 (xor, xfer intreg #1)
+ ea03dd73156703fa x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4865,7 +5585,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 9f833c9791a66c27 x13 (xor, xfer intreg #1)
+ 45086acae1f0fbe8 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4895,7 +5615,7 @@
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 39eb4f856504f7ce x13 (xor, xfer intreg #1)
+ abe7c322bde705a0 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
@@ -4917,7 +5637,7 @@
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] 7b 5d 69 f7 64 8c 79 47 6f 8f 57 84 7b c3 9c 9f
+ [112] 96 01 58 13 1a 26 4d ce 69 8a 7e ae d3 d6 ca f5
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
@@ -4947,7 +5667,7 @@
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] 42 cd cc 36 af 70 5a 49 .. .. .. .. .. .. .. ..
+ [112] 8c 9f 74 8b 6b 91 41 e0 .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
@@ -4977,7 +5697,7 @@
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] 8d 06 22 df .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] 87 86 06 ee .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
@@ -5018,8 +5738,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- eedbb4bf846226cd v17.d[0] (xor, xfer vecreg #1)
- 94094b6d188de7fa v17.d[1] (xor, xfer vecreg #1)
+ d3cd22184a47bb9d v17.d[0] (xor, xfer vecreg #1)
+ d605cfe1a39c09de v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -5048,8 +5768,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 029fcee15d9319f2 v17.d[0] (xor, xfer vecreg #1)
- 50541814802369e6 v17.d[1] (xor, xfer vecreg #1)
+ 34b6e1555effb1b9 v17.d[0] (xor, xfer vecreg #1)
+ 01020725a8723bf8 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -5078,8 +5798,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 86bcef9905c6716d v17.d[0] (xor, xfer vecreg #1)
- fa13cb2fc8681760 v17.d[1] (xor, xfer vecreg #1)
+ 5c7f1b53537e6e10 v17.d[0] (xor, xfer vecreg #1)
+ 8f71d8a1d71aaba8 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -5100,7 +5820,7 @@
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 3a fc f2 7c 33 4d e6 bb 98 8b 63 7d c8 cc ed c5
+ [144] ad 0d ad e1 5c 80 83 18 02 ab 2e 69 2a af 3c ea
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
@@ -5130,7 +5850,7 @@
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] d6 89 52 b2 c9 1c 8f 84 .. .. .. .. .. .. .. ..
+ [144] 97 67 e8 f0 19 74 5f 91 .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
@@ -5160,7 +5880,7 @@
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 61 9d 73 ee .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] f1 c7 64 85 .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
@@ -5199,8 +5919,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- f3e66911400e0ffd v17.d[0] (xor, xfer vecreg #1)
- bceee589d845dc5c v17.d[1] (xor, xfer vecreg #1)
+ eee88871503205b7 v17.d[0] (xor, xfer vecreg #1)
+ 9daa3c92e17f7ace v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -5229,8 +5949,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 476d9e9cc8b9ac0a v17.d[0] (xor, xfer vecreg #1)
- 17224cc91cc3a43e v17.d[1] (xor, xfer vecreg #1)
+ 7ff4db28862129d8 v17.d[0] (xor, xfer vecreg #1)
+ c10b90425585a4b0 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -5259,8 +5979,8 @@
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
- 20d04ccbe8ce283b v17.d[0] (xor, xfer vecreg #1)
- 22146e45c5a92bce v17.d[1] (xor, xfer vecreg #1)
+ 801fddbc0ac03507 v17.d[0] (xor, xfer vecreg #1)
+ f0ed115e260e2db5 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
@@ -5278,7 +5998,7 @@
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ...
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