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From: <sv...@va...> - 2014-08-26 18:30:55
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Author: sewardj
Date: Tue Aug 26 18:30:48 2014
New Revision: 2935
Log:
Add support for four IROps that Memcheck generates on arm64, that
the front end doesn't generate.
Modified:
trunk/priv/host_arm64_isel.c
Modified: trunk/priv/host_arm64_isel.c
==============================================================================
--- trunk/priv/host_arm64_isel.c (original)
+++ trunk/priv/host_arm64_isel.c Tue Aug 26 18:30:48 2014
@@ -2285,6 +2285,33 @@
addInstr(env, ARM64Instr_VQfromX(res, arg));
return res;
}
+ case Iop_Widen8Sto16x8: {
+ HReg res = newVRegV(env);
+ HReg arg = iselIntExpr_R(env, e->Iex.Unop.arg);
+ addInstr(env, ARM64Instr_VQfromX(res, arg));
+ addInstr(env, ARM64Instr_VBinV(ARM64vecb_ZIP18x16, res, res, res));
+ addInstr(env, ARM64Instr_VShiftImmV(ARM64vecshi_SSHR16x8,
+ res, res, 8));
+ return res;
+ }
+ case Iop_Widen16Sto32x4: {
+ HReg res = newVRegV(env);
+ HReg arg = iselIntExpr_R(env, e->Iex.Unop.arg);
+ addInstr(env, ARM64Instr_VQfromX(res, arg));
+ addInstr(env, ARM64Instr_VBinV(ARM64vecb_ZIP116x8, res, res, res));
+ addInstr(env, ARM64Instr_VShiftImmV(ARM64vecshi_SSHR32x4,
+ res, res, 16));
+ return res;
+ }
+ case Iop_Widen32Sto64x2: {
+ HReg res = newVRegV(env);
+ HReg arg = iselIntExpr_R(env, e->Iex.Unop.arg);
+ addInstr(env, ARM64Instr_VQfromX(res, arg));
+ addInstr(env, ARM64Instr_VBinV(ARM64vecb_ZIP132x4, res, res, res));
+ addInstr(env, ARM64Instr_VShiftImmV(ARM64vecshi_SSHR64x2,
+ res, res, 32));
+ return res;
+ }
/* ... */
default:
break;
@@ -3168,7 +3195,11 @@
if (e->tag == Iex_Binop) {
switch (e->Iex.Binop.op) {
-
+ case Iop_V128HLtoV256: {
+ *rHi = iselV128Expr(env, e->Iex.Binop.arg1);
+ *rLo = iselV128Expr(env, e->Iex.Binop.arg2);
+ return;
+ }
case Iop_QandSQsh64x2:
case Iop_QandSQsh32x4:
case Iop_QandSQsh16x8:
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