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From: <sv...@va...> - 2014-03-10 10:40:59
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Author: sewardj
Date: Mon Mar 10 10:40:48 2014
New Revision: 2837
Log:
Back-end handling of Iop_CmpNEZ32x4, Iop_CmpNEZ16x8, Iop_CmpNEZ8x16,
needed for Memchecking of SIMD arm64 code.
Modified:
trunk/priv/host_arm64_defs.c
trunk/priv/host_arm64_defs.h
trunk/priv/host_arm64_isel.c
Modified: trunk/priv/host_arm64_defs.c
==============================================================================
--- trunk/priv/host_arm64_defs.c (original)
+++ trunk/priv/host_arm64_defs.c Mon Mar 10 10:40:48 2014
@@ -882,6 +882,9 @@
case ARM64vecb_ORR: *nm = "orr "; *ar = "all"; return;
case ARM64vecb_XOR: *nm = "eor "; *ar = "all"; return;
case ARM64vecb_CMEQ64x2: *nm = "cmeq"; *ar = "2d"; return;
+ case ARM64vecb_CMEQ32x4: *nm = "cmeq"; *ar = "4s"; return;
+ case ARM64vecb_CMEQ16x8: *nm = "cmeq"; *ar = "8h"; return;
+ case ARM64vecb_CMEQ8x16: *nm = "cmeq"; *ar = "16b"; return;
default: vpanic("showARM64VecBinOp");
}
}
@@ -4945,7 +4948,11 @@
010 01110 10 1 m 000111 n d ORR Vd, Vn, Vm
011 01110 00 1 m 000111 n d EOR Vd, Vn, Vm
- 011 01110 11 1 m 100011 n d CMEQ Vd.2d, Vn.2d, Vm.2d
+ 011 01110 11 1 m 100011 n d CMEQ Vd.2d, Vn.2d, Vm.2d
+ 011 01110 10 1 m 100011 n d CMEQ Vd.4s, Vn.4s, Vm.4s
+ 011 01110 01 1 m 100011 n d CMEQ Vd.8h, Vn.8h, Vm.8h
+ 011 01110 00 1 m 100011 n d CMEQ Vd.16b, Vn.16b, Vm.16b
+
011 01110 11 1 m 001101 n d CMHI Vd.2d, Vn.2d, Vm.2d >u, ATC
010 01110 11 1 m 001101 n d CMGT Vd.2d, Vn.2d, Vm.2d >s, ATC
*/
@@ -5055,6 +5062,15 @@
case ARM64vecb_CMEQ64x2:
*p++ = X_3_8_5_6_5_5(X011, X01110111, vM, X100011, vN, vD);
break;
+ case ARM64vecb_CMEQ32x4:
+ *p++ = X_3_8_5_6_5_5(X011, X01110101, vM, X100011, vN, vD);
+ break;
+ case ARM64vecb_CMEQ16x8:
+ *p++ = X_3_8_5_6_5_5(X011, X01110011, vM, X100011, vN, vD);
+ break;
+ case ARM64vecb_CMEQ8x16:
+ *p++ = X_3_8_5_6_5_5(X011, X01110001, vM, X100011, vN, vD);
+ break;
default:
goto bad;
Modified: trunk/priv/host_arm64_defs.h
==============================================================================
--- trunk/priv/host_arm64_defs.h (original)
+++ trunk/priv/host_arm64_defs.h Mon Mar 10 10:40:48 2014
@@ -339,6 +339,9 @@
ARM64vecb_ORR,
ARM64vecb_XOR,
ARM64vecb_CMEQ64x2,
+ ARM64vecb_CMEQ32x4,
+ ARM64vecb_CMEQ16x8,
+ ARM64vecb_CMEQ8x16,
ARM64vecb_INVALID
}
ARM64VecBinOp;
Modified: trunk/priv/host_arm64_isel.c
==============================================================================
--- trunk/priv/host_arm64_isel.c (original)
+++ trunk/priv/host_arm64_isel.c Mon Mar 10 10:40:48 2014
@@ -4414,9 +4414,9 @@
addInstr(env, ARM64Instr_VUnaryV(op, res, arg));
return res;
}
- //ATC case Iop_CmpNEZ8x16:
- //ATC case Iop_CmpNEZ16x8:
- //ATC case Iop_CmpNEZ32x4:
+ case Iop_CmpNEZ8x16:
+ case Iop_CmpNEZ16x8:
+ case Iop_CmpNEZ32x4:
case Iop_CmpNEZ64x2: {
HReg arg = iselV128Expr(env, e->Iex.Unop.arg);
HReg zero = newVRegV(env);
@@ -4424,6 +4424,9 @@
ARM64VecBinOp cmp = ARM64vecb_INVALID;
switch (e->Iex.Unop.op) {
case Iop_CmpNEZ64x2: cmp = ARM64vecb_CMEQ64x2; break;
+ case Iop_CmpNEZ32x4: cmp = ARM64vecb_CMEQ32x4; break;
+ case Iop_CmpNEZ16x8: cmp = ARM64vecb_CMEQ16x8; break;
+ case Iop_CmpNEZ8x16: cmp = ARM64vecb_CMEQ8x16; break;
default: vassert(0);
}
// This is pretty feeble. Better: use CMP against zero
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