|
From: <sv...@va...> - 2014-02-27 14:17:35
|
Author: dejanj
Date: Thu Feb 27 14:17:19 2014
New Revision: 2827
Log:
mips32: Fpu guest registers are ULong and the initial values need to be
extended.
Because we are supporting both big and little endian mips32 we need to
make sure that the initial values for the fpu registers are the same for both
endian.
Modified:
trunk/priv/guest_mips_helpers.c
Modified: trunk/priv/guest_mips_helpers.c
==============================================================================
--- trunk/priv/guest_mips_helpers.c (original)
+++ trunk/priv/guest_mips_helpers.c Thu Feb 27 14:17:19 2014
@@ -105,38 +105,38 @@
vex_state->guest_LO = 0; /* Multiply and divide register lower result */
/* FPU Registers */
- vex_state->guest_f0 = 0x7ff80000; /* Floting point general purpose registers */
- vex_state->guest_f1 = 0x7ff80000;
- vex_state->guest_f2 = 0x7ff80000;
- vex_state->guest_f3 = 0x7ff80000;
- vex_state->guest_f4 = 0x7ff80000;
- vex_state->guest_f5 = 0x7ff80000;
- vex_state->guest_f6 = 0x7ff80000;
- vex_state->guest_f7 = 0x7ff80000;
- vex_state->guest_f8 = 0x7ff80000;
- vex_state->guest_f9 = 0x7ff80000;
- vex_state->guest_f10 = 0x7ff80000;
- vex_state->guest_f11 = 0x7ff80000;
- vex_state->guest_f12 = 0x7ff80000;
- vex_state->guest_f13 = 0x7ff80000;
- vex_state->guest_f14 = 0x7ff80000;
- vex_state->guest_f15 = 0x7ff80000;
- vex_state->guest_f16 = 0x7ff80000;
- vex_state->guest_f17 = 0x7ff80000;
- vex_state->guest_f18 = 0x7ff80000;
- vex_state->guest_f19 = 0x7ff80000;
- vex_state->guest_f20 = 0x7ff80000;
- vex_state->guest_f21 = 0x7ff80000;
- vex_state->guest_f22 = 0x7ff80000;
- vex_state->guest_f23 = 0x7ff80000;
- vex_state->guest_f24 = 0x7ff80000;
- vex_state->guest_f25 = 0x7ff80000;
- vex_state->guest_f26 = 0x7ff80000;
- vex_state->guest_f27 = 0x7ff80000;
- vex_state->guest_f28 = 0x7ff80000;
- vex_state->guest_f29 = 0x7ff80000;
- vex_state->guest_f30 = 0x7ff80000;
- vex_state->guest_f31 = 0x7ff80000;
+ vex_state->guest_f0 = 0x7ff800007ff80000; /* Floting point GP registers */
+ vex_state->guest_f1 = 0x7ff800007ff80000;
+ vex_state->guest_f2 = 0x7ff800007ff80000;
+ vex_state->guest_f3 = 0x7ff800007ff80000;
+ vex_state->guest_f4 = 0x7ff800007ff80000;
+ vex_state->guest_f5 = 0x7ff800007ff80000;
+ vex_state->guest_f6 = 0x7ff800007ff80000;
+ vex_state->guest_f7 = 0x7ff800007ff80000;
+ vex_state->guest_f8 = 0x7ff800007ff80000;
+ vex_state->guest_f9 = 0x7ff800007ff80000;
+ vex_state->guest_f10 = 0x7ff800007ff80000;
+ vex_state->guest_f11 = 0x7ff800007ff80000;
+ vex_state->guest_f12 = 0x7ff800007ff80000;
+ vex_state->guest_f13 = 0x7ff800007ff80000;
+ vex_state->guest_f14 = 0x7ff800007ff80000;
+ vex_state->guest_f15 = 0x7ff800007ff80000;
+ vex_state->guest_f16 = 0x7ff800007ff80000;
+ vex_state->guest_f17 = 0x7ff800007ff80000;
+ vex_state->guest_f18 = 0x7ff800007ff80000;
+ vex_state->guest_f19 = 0x7ff800007ff80000;
+ vex_state->guest_f20 = 0x7ff800007ff80000;
+ vex_state->guest_f21 = 0x7ff800007ff80000;
+ vex_state->guest_f22 = 0x7ff800007ff80000;
+ vex_state->guest_f23 = 0x7ff800007ff80000;
+ vex_state->guest_f24 = 0x7ff800007ff80000;
+ vex_state->guest_f25 = 0x7ff800007ff80000;
+ vex_state->guest_f26 = 0x7ff800007ff80000;
+ vex_state->guest_f27 = 0x7ff800007ff80000;
+ vex_state->guest_f28 = 0x7ff800007ff80000;
+ vex_state->guest_f29 = 0x7ff800007ff80000;
+ vex_state->guest_f30 = 0x7ff800007ff80000;
+ vex_state->guest_f31 = 0x7ff800007ff80000;
vex_state->guest_FIR = 0; /* FP implementation and revision register */
vex_state->guest_FCCR = 0; /* FP condition codes register */
|