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From: Anil S. <ani...@li...> - 2014-02-21 13:09:45
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Hi Julian,
I will try that. There is a "dc zva, x8" instruction as well in the ld*.so
that is causing another unrecognized instruction error.
Does this mean valgrind will not emulate the dc instruction (i.e. all
variants of it) at all?
Thanks,
Anil
On 21 February 2014 15:18, Julian Seward <js...@ac...> wrote:
>
> > I used the attached patch to address the issued with the DCZID_EL0
> > register, since we want this to be supported.
>
> I am a bit surprised that this patch works for you, since
>
> (1) it changes the size of VexGuestARM64State and I would therefore
> expect to get an assertion failure indicating that the size is
> no longer a multiple of 16, and
>
> (2) IIUC, it allows DCZID_EL0<4> == 0, which means the DC ZVA
> instruction is permitted, but VEX does not handle that instruction.
>
> Can you instead try the patch below and see if it helps?
>
> J
>
>
> Index: priv/guest_arm64_toIR.c
> ===================================================================
> --- priv/guest_arm64_toIR.c (revision 2823)
> +++ priv/guest_arm64_toIR.c (working copy)
> @@ -4368,6 +4368,18 @@
> }
> return True;
> }
> + /* Cases for DCZID_EL0
> + Don't support arbitrary reads and writes to this register. Just
> + return the value 16, which indicates that the DC ZVA instruction
> + is not permitted, so we don't have to emulate it.
> + D5 3B 00 111 Rt MRS rT, dczid_el0
> + */
> + if ((INSN(31,0) & 0xFFFFFFE0) == 0xD53B00E0) {
> + UInt tt = INSN(4,0);
> + putIReg64orZR(tt, mkU64(1<<4));
> + DIP("mrs %s, dczid_el0 (FAKED)\n", nameIReg64orZR(tt));
> + return True;
> + }
>
> /* FIXME Temporary hacks to get through ld.so FIXME */
> /* ------------------ ISB ------------------ */
>
>
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