[Valgrind-developers] Finalising for a 3.9.0 release

[Julian S. <js...@ac...>]

It's well overdue for another release.  I propose to release 3.9.0 on
the last day of October, Thursday 31st, so we really need to have the
trunk stable for branching by the 15th.

There is a huge list of open bugs to choose from, far more than we
have resources to fix.  There's a fairly up to date summary in the
trunk, in docs/internals/3_8_BUGSTATUS.txt.  Please look there for
the overall top level current state.

Here are the ones I'd really like to have fixed for the release.  More
than half of these have patches attached, which just need to be checked
over and committed.  Please take some of these and land or fix them, if
they fall in your area of expertise.  I will make a start by landing the
ARM/Thumb ones.

307557  Leaks on Mac OS X 10.7.5 libraries at ImageLoader::recursiveInit[..]
308135  PPC32 MPC8xx has 16 bytes cache size
289578  Backtraces with ARM unwind tables (stack scan flags) (/me to take)
243232  Inconsistent Lock Orderings report with trylock (PBOS?)
309827  add support for nvidia (nvmem) ioctls
318050  libmpiwrap fails to compile with out-of-source build
320131  WARNING: unhandled syscall: 369 on ARM (prlimit64)
320661  vgModuleLocal_read_elf_debug_info(): "Assertion '!di->soname'
320998  vex amd64->IR pcmpestri and pcmpestrm SSE4.2 instruction (easy)
321888  Unhandled instruction: LDRH (Thumb)
321891  Unhandled instruction: LDRHT (Thumb)
321892  Unhandled instruction: LDRSH (Thumb)
321902  disInstr(ARM): 0xECECA102
322254  Show threadname together with tid if set by application
322563  vex mips->IR: unhandled instruction bytes: 0x70 0x83 0xF0 0x3A
323035  Unhandled instruction: LDRSHT(Thumb)
323036  Unhandled instruction: SMMLS (ARM and Thumb)
323175  Unhandled instruction: SMLALD (ARM + Thumb)
323177  Unhandled instruction: SMLSLD (ARM + Thumb)
323178  Unhandled instruction: PLDW register (ARM)
323179  Unhandled instruction: PLDW immediate (ARM)
323432  Calling pthread_cond_destroy() or pthread_mutex_destroy()
323777  Documentation does not warn of sgcheck+darwin incompatibility
323803  Transactional memory instructions are not supported for Power
324047  Valgrind doesn't support [LDR,ST]{S}[B,H]T ARM instructions
324149  helgrind: When pthread_cond_timedwait returns ETIMEDOUT, helgrind
324181  mmap does not handle MAP_32BIT
324421  Support for fanotify API on ARM architecture
324834  Unhandled instructions in Microsoft C run-time for x86_64 (easy)
324894  Phase 3 support for IBM Power ISA 2.07

Other fixes that I'd like to ship:

* There's been some discussion on the users list, about Helgrind's
  lock order checker giving false reports in the case of trylocks.
  There may be a simple fix.  243232 is an example of this.  PBos?

* Support for Haswell RTM (restricted transactional memory insns) is
  in, but Haswell HLE isn't supported yet.  To make this work requires
  the x86_64 insn decoder to accept XACQUIRE/XRELEASE prefixes (F2/F3)
  on certain memory instructions as listed by the Intel documentation.
  Should be easy.

* Initial support for Power TM instructions needs to land (323803).
  CarlL is on the case, I think.

* Syscall/Mach trap/ioctl tidyups for OSX10.8, if fixes appear in
  time.

Apart from that, testing on recent distros and with the latest GCCs
and glibcs would be helpful.  I'd particularly like to know that it
works OK on cutting edge Fedora on as many architectures as we can
test.  Testing on recent Android release would also be appreciated.

Anything critical that I forgot?

J