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[Valgrind-developers] [PATCH RFC] Power PC Transactional Memory Support
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From: Carl E. L. <ce...@li...> - 2013-07-11 14:33:52
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Julian:
I have the following patch for the Power PC to implement that implements you first suggested
approach for handling the Transactional Memory instructions. I just wanted to throw it out there for
people to look at and comment on. I am working on implementing you second suggestion. I have tested
this patch with a very simple TM example as given below. The patch causes the execution flow to take
the TM failure path as expected. The compiler is generating a branch if not equal to decide if it
should take the TM path or the failure path. For now, the Valgrind patch just assumes the compiler
will always generate the branch if not equal instruction to take one of the two paths. Furthermore,
it is assumed there will always be a failure path. I need to talk with Peter when he gets back about
the code generated by the compiler to determine if the compiler might generate different code
sequences.
Again, this patch is just for discussion as to how the first suggested TM approach might be implemented
on Power.
Carl Love
-------------------------------------------------------------------------------------------------
Test case:
#include <stdio.h>
int
__attribute__ ((noinline))
htm_begin (int r3, int r4)
{
int ret;
if (__builtin_tbegin (0))
{
ret = r3;
__builtin_tend (0);
}
else
{
ret = r4;
}
return ret;
}
int main (void)
{
int ret;
ret = htm_begin (10, 20);
printf ("ret = %d, expected = 10\n", ret);
return 0;
}
-------------------------------------------------------------------------------------------------
Power PC, add Transactional Memory instruction support
The following Transactional Memory instructions are added:
tbegin., tend., tsr., tcheck., tabortwc.,
tabortdc., tabortwci., tabortdci., tabort.
The patch implements the first proposal by Julian on how to handle the
TM instructions. The assumption is that there is always an error handler
for the tbegin instruction. The tbegin support modifies the condition code
register to set the TM failure thus causing the conditional branch instruction
that follows the tbegin to take the failure path. The other TM instructions
are all treated as no ops as we shouldn't be executing the transactiona
code path.
Signed-off-by: Carl Love <ce...@us...>
---
VEX/priv/guest_ppc_helpers.c | 10 +-
VEX/priv/guest_ppc_toIR.c | 272 ++++++++++++++++++++++++++++++++++++++++++-
VEX/pub/libvex_guest_ppc32.h | 8 +-
VEX/pub/libvex_guest_ppc64.h | 10 +-
4 files changed, 292 insertions(+), 8 deletions(-)
diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c
index f320149..c326453 100644
--- a/VEX/priv/guest_ppc_helpers.c
+++ b/VEX/priv/guest_ppc_helpers.c
@@ -511,7 +511,9 @@ void LibVEX_GuestPPC32_initialise ( /*OUT*/VexGuestPPC32State* vex_state )
vex_state->guest_IP_AT_SYSCALL = 0;
vex_state->guest_SPRG3_RO = 0;
- vex_state->padding = 0;
+ vex_state->padding1 = 0;
+ vex_state->padding2 = 0;
+ vex_state->padding3 = 0;
}
@@ -676,10 +678,14 @@ void LibVEX_GuestPPC64_initialise ( /*OUT*/VexGuestPPC64State* vex_state )
vex_state->guest_IP_AT_SYSCALL = 0;
vex_state->guest_SPRG3_RO = 0;
+ vex_state->guest_TFHAR = 0xa1b2c3d4;
+ vex_state->guest_TFIAR = 0xf7e6d5c4;
+ vex_state->guest_TEXASR = 0x1f2e3d4c5b6a7988;
- vex_state->padding2 = 0;
+ /* vex_state->padding2 = 0;
vex_state->padding3 = 0;
vex_state->padding4 = 0;
+ */
}
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index d46512a..7b98535 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -232,7 +232,9 @@ static void* fnptr_to_fnentry( VexAbiInfo* vbi, void* f )
#define OFFB_TILEN offsetofPPCGuestState(guest_TILEN)
#define OFFB_NRADDR offsetofPPCGuestState(guest_NRADDR)
#define OFFB_NRADDR_GPR2 offsetofPPCGuestState(guest_NRADDR_GPR2)
-
+#define OFFB_TFHAR offsetofPPCGuestState(guest_TFHAR)
+#define OFFB_TEXASR offsetofPPCGuestState(guest_TEXASR)
+#define OFFB_TFIAR offsetofPPCGuestState(guest_TFIAR)
/*------------------------------------------------------------*/
/*--- Extract instruction fields --- */
@@ -378,6 +380,9 @@ typedef enum {
PPC_GST_TILEN, // For icbi: length of area to invalidate
PPC_GST_IP_AT_SYSCALL, // the CIA of the most recently executed SC insn
PPC_GST_SPRG3_RO, // SPRG3
+ PPC_GST_TFHAR, // Transactional Failure Handler Address Register
+ PPC_GST_TFIAR, // Transactional Failure Instruction Address Register
+ PPC_GST_TEXASR, // Transactional EXception And Summary Register
PPC_GST_MAX
} PPC_GST;
@@ -1308,6 +1313,12 @@ static IRExpr* getVReg ( UInt archreg )
static void putVReg ( UInt archreg, IRExpr* e )
{
vassert(archreg < 32);
+ if (typeOfIRExpr(irsb->tyenv, e) != Ity_V128) {
+ vex_printf("putVReg type of expr is ");
+ ppIRType(typeOfIRExpr(irsb->tyenv, e) );
+ vex_printf(" not Ity_V128 as expected.\n");
+ }
+
vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_V128);
stmt( IRStmt_Put(vectorGuestRegOffset(archreg), e) );
}
@@ -2530,6 +2541,15 @@ static IRExpr* /* :: Ity_I32/64 */ getGST ( PPC_GST reg )
binop( Iop_Shl32, getXER_CA32(), mkU8(29)),
getXER_BC32()));
+ case PPC_GST_TFHAR:
+ return IRExpr_Get( OFFB_TFHAR, ty );
+
+ case PPC_GST_TEXASR:
+ return IRExpr_Get( OFFB_TEXASR, ty );
+
+ case PPC_GST_TFIAR:
+ return IRExpr_Get( OFFB_TFIAR, ty );
+
default:
vex_printf("getGST(ppc): reg = %u", reg);
vpanic("getGST(ppc)");
@@ -2691,6 +2711,18 @@ static void putGST ( PPC_GST reg, IRExpr* src )
stmt( IRStmt_Put( OFFB_TILEN, src) );
break;
+ case PPC_GST_TEXASR:
+ vassert( ty_src == ty );
+ stmt( IRStmt_Put( OFFB_TEXASR, src ) );
+ break;
+ case PPC_GST_TFIAR:
+ vassert( ty_src == ty );
+ stmt( IRStmt_Put( OFFB_TFIAR, src ) );
+ break;
+ case PPC_GST_TFHAR:
+ vassert( ty_src == ty );
+ stmt( IRStmt_Put( OFFB_TFHAR, src ) );
+ break;
default:
vex_printf("putGST(ppc): reg = %u", reg);
vpanic("putGST(ppc)");
@@ -3007,6 +3039,50 @@ static IRTemp getNegatedResult_32(IRTemp intermediateResult)
}
/*------------------------------------------------------------*/
+/* Transactional memory helpers
+ *
+ *------------------------------------------------------------*/
+
+static unsigned long long generate_TMreason( UInt failure_code,
+ UInt persistant,
+ UInt nest_overflow,
+ UInt tm_exact )
+{
+ unsigned long long tm_err_code =
+ ( (ULong) 0) << (63-6) /* Failure code */
+ | ( (ULong) persistant) << (63-7) /* Failure persistant */
+ | ( (ULong) 0) << (63-8) /* Disallowed */
+ | ( (ULong) nest_overflow) << (63-9) /* Nesting Overflow */
+ | ( (ULong) 0) << (63-10) /* Footprint Overflow */
+ | ( (ULong) 0) << (63-11) /* Self-Induced Conflict */
+ | ( (ULong) 0) << (63-12) /* Non-Transactional Conflict */
+ | ( (ULong) 0) << (63-13) /* Transactional Conflict */
+ | ( (ULong) 0) << (63-14) /* Translation Invalidation Conflict */
+ | ( (ULong) 0) << (63-15) /* Implementation-specific */
+ | ( (ULong) 0) << (63-16) /* Instruction Fetch Conflict */
+ | ( (ULong) 0) << (63-30) /* Reserved */
+ | ( (ULong) 0) << (63-31) /* Abort */
+ | ( (ULong) 0) << (63-32) /* Suspend */
+ | ( (ULong) 0) << (63-33) /* Reserved */
+ | ( (ULong) 0) << (63-35) /* Privilege */
+ | ( (ULong) 0) << (63-36) /* Failure Summary */
+ | ( (ULong) tm_exact) << (63-37) /* TFIAR Exact */
+ | ( (ULong) 0) << (63-38) /* ROT */
+ | ( (ULong) 0) << (63-51) /* Reserved */
+ | ( (ULong) 0) << (63-63); /* Transaction Level */
+
+ return tm_err_code;
+}
+
+static void storeTMfailure( Addr64 err_address, ULong tm_reason,
+ Addr64 handler_address )
+{
+ putGST( PPC_GST_TFIAR, mkU64( err_address ) );
+ putGST( PPC_GST_TEXASR, mkU64( tm_reason ) );
+ putGST( PPC_GST_TFHAR, mkU64( handler_address ) );
+}
+
+/*------------------------------------------------------------*/
/*--- Integer Instruction Translation --- */
/*------------------------------------------------------------*/
@@ -6652,6 +6728,18 @@ static Bool dis_proc_ctl ( VexAbiInfo* vbi, UInt theInstr )
DIP("mfctr r%u\n", rD_addr);
putIReg( rD_addr, getGST( PPC_GST_CTR ) );
break;
+ case 0x80: // 128
+ DIP("mfspr r%u (TFHAR)\n", rD_addr);
+ putIReg( rD_addr, getGST( PPC_GST_TFHAR) );
+ break;
+ case 0x81: // 129
+ DIP("mfspr r%u (TFIAR)\n", rD_addr);
+ putIReg( rD_addr, getGST( PPC_GST_TFIAR) );
+ break;
+ case 0x82: // 130
+ DIP("mfspr r%u (TEXASR)\n", rD_addr);
+ putIReg( rD_addr, getGST( PPC_GST_TEXASR) );
+ break;
case 0x100:
DIP("mfvrsave r%u\n", rD_addr);
putIReg( rD_addr, mkWidenFrom32(ty, getGST( PPC_GST_VRSAVE ),
@@ -6796,7 +6884,18 @@ static Bool dis_proc_ctl ( VexAbiInfo* vbi, UInt theInstr )
DIP("mtvrsave r%u\n", rS_addr);
putGST( PPC_GST_VRSAVE, mkNarrowTo32(ty, mkexpr(rS)) );
break;
-
+ case 0x80: // 128
+ DIP("mtspr r%u (TFHAR)\n", rS_addr);
+ putGST( PPC_GST_TFHAR, mkexpr(rS) );
+ break;
+ case 0x81: // 129
+ DIP("mtspr r%u (TFIAR)\n", rS_addr);
+ putGST( PPC_GST_TFIAR, mkexpr(rS) );
+ break;
+ case 0x82: // 130
+ DIP("mtspr r%u (TEXASR)\n", rS_addr);
+ putGST( PPC_GST_TEXASR, mkexpr(rS) );
+ break;
default:
vex_printf("dis_proc_ctl(ppc)(mtspr,SPR)(%u)\n", SPR);
return False;
@@ -17314,6 +17413,164 @@ static Bool dis_av_fp_convert ( UInt theInstr )
return True;
}
+static Bool dis_transactional_memory ( UInt theInstr, UInt nextInstr,
+ VexAbiInfo* vbi,
+ /*OUT*/DisResult* dres,
+ Bool (*resteerOkFn)(void*,Addr64),
+ void* callback_opaque )
+{
+ UInt opc2 = IFIELD( theInstr, 1, 10 );
+ UInt opc1_next = ifieldOPC(nextInstr);
+
+ switch (opc2) {
+ case 0x28E: { //tbegin.
+ /* The current implementation is to just fail the tbegin and execute
+ * the failure path. The failure path is assumed to be functionaly
+ * equivalent to the transactional path with the needed data locking
+ * to ensure correctness. The tend is just a noop and shouldn't
+ * actually get executed. The instruction following the tbegin is
+ * expected to be a branch to the failure path.
+ */
+ UInt R = IFIELD( theInstr, 21, 1 );
+
+ DIP("tbegin. %d\n", R);
+ if (opc1_next == 0x10) { // conditional branch
+ ULong tm_reason;
+ UInt failure_code = 0; /* Forcing failure, will not be due to tabort
+ * or treclaim.
+ */
+ UInt persistant = 1; /* set persistant since we are always failing
+ * the tbegin.
+ */
+ UInt nest_overflow = 1; /* Alowed nesting depth overflow, we use this
+ as the reason for failing the trasaction */
+ UInt tm_exact = 1; /* have exact address for failure */
+ UChar flag_AA = ifieldBIT1(nextInstr);
+ UInt BD_u16 = ifieldUIMM16(nextInstr) & 0xFFFFFFFC; /* mask off */
+ Addr64 failure_tgt = 0;
+ IRType ty = mode64 ? Ity_I64 : Ity_I32;
+
+ /* Get the address of the failure handler from the conditional
+ * branch in the next instruction location.
+ */
+ if ( flag_AA )
+ failure_tgt = mkSzAddr( ty, extend_s_16to64( BD_u16 ) );
+ else
+ failure_tgt = mkSzAddr( ty, guest_CIA_curr_instr +
+ (Long)extend_s_16to64( BD_u16 ) );
+
+ /* Set the CR0 field to indicate the tbegin failed. Then let
+ * the code do the branch to the failure path.
+ *
+ * 000 || 0 Transaction initiation successful,
+ * unnested (Transaction state of
+ * Non-transactional prior to tbegin.)
+ * 010 || 0 Transaction initiation successful, nested
+ * (Transaction state of Transactional
+ * prior to tbegin.)
+ * 001 || 0 Transaction initiation unsuccessful,
+ * (Transaction state of Suspended prior
+ * to tbegin.)
+ */
+ if (mode64)
+ /* 0x0010 takes transactional path */
+ /* 0x0000 takes the failure path */
+ set_CR0(mkU64(0x0000));
+ else
+ set_CR0(mkU32(0x0000));
+
+ tm_reason = generate_TMreason( failure_code, persistant,
+ nest_overflow, tm_exact );
+ storeTMfailure( guest_CIA_curr_instr, tm_reason, failure_tgt );
+ return True;
+
+ } else {
+ vex_printf("dis_transactional_memory(ppc): tbegin not followed by a conditional branch instruction, instruction 0x%x\n", nextInstr);
+ return False;
+ }
+ break;
+ }
+
+ case 0x2AE: { //tend.
+ /* The tend. is just a noop. Do nothing */
+ UInt A = IFIELD( theInstr, 25, 1 );
+
+ DIP("tend. %d\n", A);
+ break;
+ }
+
+ case 0x2EE: { //tsr.
+ /* The tsr. is just a noop. Do nothing */
+ UInt L = IFIELD( theInstr, 21, 1 );
+
+ DIP("tsr. %d\n", L);
+ break;
+ }
+
+ case 0x2CE: { //tcheck.
+ /* The tcheck. is just a noop. Do nothing */
+ UInt BF = IFIELD( theInstr, 25, 1 );
+
+ DIP("tcheck. %d\n", BF);
+ break;
+ }
+
+ case 0x30E: { //tbortwc.
+ /* The tabortwc. is just a noop. Do nothing */
+ UInt TO = IFIELD( theInstr, 25, 1 );
+ UInt RA = IFIELD( theInstr, 16, 5 );
+ UInt RB = IFIELD( theInstr, 11, 5 );
+
+ DIP("tabortwc. %d,%d,%d\n", TO, RA, RB);
+ break;
+ }
+
+ case 0x32E: { //tbortdc.
+ /* The tabortdc. is just a noop. Do nothing */
+ UInt TO = IFIELD( theInstr, 25, 1 );
+ UInt RA = IFIELD( theInstr, 16, 5 );
+ UInt RB = IFIELD( theInstr, 11, 5 );
+
+ DIP("tabortdc. %d,%d,%d\n", TO, RA, RB);
+ break;
+ }
+
+ case 0x34E: { //tbortwci.
+ /* The tabortwci. is just a noop. Do nothing */
+ UInt TO = IFIELD( theInstr, 25, 1 );
+ UInt RA = IFIELD( theInstr, 16, 5 );
+ UInt SI = IFIELD( theInstr, 11, 5 );
+
+ DIP("tabortwci. %d,%d,%d\n", TO, RA, SI);
+ break;
+ }
+
+ case 0x36E: { //tbortdci.
+ /* The tabortdci. is just a noop. Do nothing */
+ UInt TO = IFIELD( theInstr, 25, 1 );
+ UInt RA = IFIELD( theInstr, 16, 5 );
+ UInt SI = IFIELD( theInstr, 11, 5 );
+
+ DIP("tabortdci. %d,%d,%d\n", TO, RA, SI);
+ break;
+ }
+
+ case 0x38E: { //tbort.
+ /* The tabort. is just a noop. Do nothing */
+ UInt RA = IFIELD( theInstr, 16, 5 );
+
+ DIP("tabort. %d\n", RA);
+ break;
+ }
+
+ default:
+ vex_printf("dis_transactional_memory(ppc): unrecognized instruction\n");
+ return False;
+ }
+
+ return True;
+}
+
/* The 0x3C primary opcode (VSX category) uses several different forms of
* extended opcodes:
@@ -18403,6 +18660,17 @@ DisResult disInstr_PPC_WRK (
if (dis_int_logic( theInstr )) goto decode_success;
goto decode_failure;
+ case 0x28E: case 0x2AE: // tbegin., tend.
+ case 0x2EE: case 0x2CE: case 0x30E: // tsr., tcheck., tabortwc.
+ case 0x32E: case 0x34E: case 0x36E: // tabortdc., tabortwci., tabortdci.
+ case 0x38E: // tabort.
+ if (dis_transactional_memory( theInstr,
+ getUIntBigendianly( (UChar*)(&guest_code[delta + 4])),
+ abiinfo, &dres,
+ resteerOkFn, callback_opaque))
+ goto decode_success;
+ goto decode_failure;
+
/* 64bit Integer Logical Instructions */
case 0x3DA: case 0x03A: // extsw, cntlzd
if (!mode64) goto decode_failure;
diff --git a/VEX/pub/libvex_guest_ppc32.h b/VEX/pub/libvex_guest_ppc32.h
index d90b7d3..e07e80d 100644
--- a/VEX/pub/libvex_guest_ppc32.h
+++ b/VEX/pub/libvex_guest_ppc32.h
@@ -238,8 +238,14 @@ typedef
threading on AIX. */
/* 1352 */ UInt guest_SPRG3_RO;
+ /* 1360 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register
+ /* 1368 */ ULong guest_TEXASR; // Transaction EXception And Summary Register
+ /* 1376 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register
+
/* Padding to make it have an 8-aligned size */
- /* 1356 */ UInt padding;
+ /* 1380 */ UInt padding1;
+ /* 1384 */ UInt padding2;
+ /* 1388 */ UInt padding3;
}
VexGuestPPC32State;
diff --git a/VEX/pub/libvex_guest_ppc64.h b/VEX/pub/libvex_guest_ppc64.h
index 1c9502c..531e92d 100644
--- a/VEX/pub/libvex_guest_ppc64.h
+++ b/VEX/pub/libvex_guest_ppc64.h
@@ -279,11 +279,15 @@ typedef
threading on AIX. */
/* 1648 */ ULong guest_SPRG3_RO;
+ /* 1656 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register
+ /* 1684 */ ULong guest_TEXASR; // Transaction EXception And Summary Register
+ /* 1692 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register
+
/* offsets in comments are wrong ..*/
/* Padding to make it have an 16-aligned size */
- /* 1656 */ ULong padding2;
- /* 16XX */ ULong padding3;
- /* 16XX */ ULong padding4;
+ /* 1656 ULong padding2; */
+ /* 16XX ULong padding3; */
+ /* 16XX ULong padding4; */
}
VexGuestPPC64State;
--
1.7.12.rc1.22.gbfbf4d4
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