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From: <sv...@va...> - 2012-11-23 00:44:44
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petarj 2012-11-23 00:44:37 +0000 (Fri, 23 Nov 2012)
New Revision: 2565
Log:
Correctly model LL/SC on MIPS.
As the issue with RMW on MIPS does not block execution anymore (see Valgrind
patch r13136), we can switch back to model it through LoadL and StoreC instead
of using incorrect Load and Store.
This will give back correct output to memcheck/tests/atomic_incs on MIPS.
Modified files:
trunk/priv/host_mips_isel.c
Modified: trunk/priv/host_mips_isel.c (+6 -6)
===================================================================
--- trunk/priv/host_mips_isel.c 2012-11-21 00:36:55 +00:00 (rev 2564)
+++ trunk/priv/host_mips_isel.c 2012-11-23 00:44:37 +00:00 (rev 2565)
@@ -2954,10 +2954,10 @@
HReg r_dst = lookupIRTemp(env, res);
if (tyRes == Ity_I32) {
- addInstr(env, MIPSInstr_Load(4, r_dst, r_addr, mode64));
+ addInstr(env, MIPSInstr_LoadL(4, r_dst, r_addr, mode64));
return;
} else if (tyRes == Ity_I64 && mode64) {
- addInstr(env, MIPSInstr_Load(8, r_dst, r_addr, mode64));
+ addInstr(env, MIPSInstr_LoadL(8, r_dst, r_addr, mode64));
return;
}
/* fallthru */ ;
@@ -2971,12 +2971,12 @@
stmt->Ist.LLSC.storedata);
if (tyData == Ity_I32) {
- addInstr(env, MIPSInstr_Store(4, r_addr, r_src, mode64));
- addInstr(env, MIPSInstr_LI(r_dst, 0x1));
+ addInstr(env, mk_iMOVds_RR(r_dst, r_src));
+ addInstr(env, MIPSInstr_StoreC(4, r_addr, r_dst, mode64));
return;
} else if (tyData == Ity_I64 && mode64) {
- addInstr(env, MIPSInstr_Store(8, r_addr, r_src, mode64));
- addInstr(env, MIPSInstr_LI(r_dst, 0x1));
+ addInstr(env, mk_iMOVds_RR(r_dst, r_src));
+ addInstr(env, MIPSInstr_StoreC(8, r_addr, r_dst, mode64));
return;
}
/* fallthru */
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