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From: <sv...@va...> - 2012-11-21 00:37:05
|
florian 2012-11-21 00:36:55 +0000 (Wed, 21 Nov 2012)
New Revision: 2564
Log:
Changes for -Wwrite-strings
Modified files:
trunk/priv/guest_amd64_toIR.c
trunk/priv/guest_arm_toIR.c
trunk/priv/guest_generic_bb_to_IR.c
trunk/priv/guest_ppc_toIR.c
trunk/priv/guest_s390_toIR.c
trunk/priv/guest_x86_toIR.c
trunk/priv/host_amd64_defs.c
trunk/priv/host_amd64_defs.h
trunk/priv/host_arm_defs.c
trunk/priv/host_arm_defs.h
trunk/priv/host_generic_regs.c
trunk/priv/host_mips_defs.c
trunk/priv/host_mips_defs.h
trunk/priv/host_ppc_defs.c
trunk/priv/host_ppc_defs.h
trunk/priv/host_s390_defs.c
trunk/priv/host_x86_defs.c
trunk/priv/host_x86_defs.h
trunk/priv/main_main.c
trunk/priv/main_util.c
trunk/priv/s390_disasm.c
Modified: trunk/priv/host_generic_regs.c (+2 -2)
===================================================================
--- trunk/priv/host_generic_regs.c 2012-11-20 17:32:48 +00:00 (rev 2563)
+++ trunk/priv/host_generic_regs.c 2012-11-21 00:36:55 +00:00 (rev 2564)
@@ -56,7 +56,7 @@
/* Generic printing for registers. */
void ppHReg ( HReg r )
{
- HChar* maybe_v = hregIsVirtual(r) ? "v" : "";
+ const HChar* maybe_v = hregIsVirtual(r) ? "v" : "";
Int regNo = hregNumber(r);
switch (hregClass(r)) {
case HRcInt32: vex_printf("%%%sr%d", maybe_v, regNo); return;
@@ -77,7 +77,7 @@
void ppHRegUsage ( HRegUsage* tab )
{
Int i;
- HChar* str;
+ const HChar* str;
vex_printf("HRegUsage {\n");
for (i = 0; i < tab->n_used; i++) {
switch (tab->mode[i]) {
Modified: trunk/priv/guest_x86_toIR.c (+69 -69)
===================================================================
--- trunk/priv/guest_x86_toIR.c 2012-11-20 17:32:48 +00:00 (rev 2563)
+++ trunk/priv/guest_x86_toIR.c 2012-11-21 00:36:55 +00:00 (rev 2564)
@@ -1059,7 +1059,7 @@
/* Condition codes, using the Intel encoding. */
-static HChar* name_X86Condcode ( X86Condcode cond )
+static const HChar* name_X86Condcode ( X86Condcode cond )
{
switch (cond) {
case X86CondO: return "o";
@@ -1226,54 +1226,54 @@
/* -------------- Helpers for disassembly printing. -------------- */
-static HChar* nameGrp1 ( Int opc_aux )
+static const HChar* nameGrp1 ( Int opc_aux )
{
- static HChar* grp1_names[8]
+ static const HChar* grp1_names[8]
= { "add", "or", "adc", "sbb", "and", "sub", "xor", "cmp" };
if (opc_aux < 0 || opc_aux > 7) vpanic("nameGrp1(x86)");
return grp1_names[opc_aux];
}
-static HChar* nameGrp2 ( Int opc_aux )
+static const HChar* nameGrp2 ( Int opc_aux )
{
- static HChar* grp2_names[8]
+ static const HChar* grp2_names[8]
= { "rol", "ror", "rcl", "rcr", "shl", "shr", "shl", "sar" };
if (opc_aux < 0 || opc_aux > 7) vpanic("nameGrp2(x86)");
return grp2_names[opc_aux];
}
-static HChar* nameGrp4 ( Int opc_aux )
+static const HChar* nameGrp4 ( Int opc_aux )
{
- static HChar* grp4_names[8]
+ static const HChar* grp4_names[8]
= { "inc", "dec", "???", "???", "???", "???", "???", "???" };
if (opc_aux < 0 || opc_aux > 1) vpanic("nameGrp4(x86)");
return grp4_names[opc_aux];
}
-static HChar* nameGrp5 ( Int opc_aux )
+static const HChar* nameGrp5 ( Int opc_aux )
{
- static HChar* grp5_names[8]
+ static const HChar* grp5_names[8]
= { "inc", "dec", "call*", "call*", "jmp*", "jmp*", "push", "???" };
if (opc_aux < 0 || opc_aux > 6) vpanic("nameGrp5(x86)");
return grp5_names[opc_aux];
}
-static HChar* nameGrp8 ( Int opc_aux )
+static const HChar* nameGrp8 ( Int opc_aux )
{
- static HChar* grp8_names[8]
+ static const HChar* grp8_names[8]
= { "???", "???", "???", "???", "bt", "bts", "btr", "btc" };
if (opc_aux < 4 || opc_aux > 7) vpanic("nameGrp8(x86)");
return grp8_names[opc_aux];
}
-static HChar* nameIReg ( Int size, Int reg )
+static const HChar* nameIReg ( Int size, Int reg )
{
- static HChar* ireg32_names[8]
+ static const HChar* ireg32_names[8]
= { "%eax", "%ecx", "%edx", "%ebx",
"%esp", "%ebp", "%esi", "%edi" };
- static HChar* ireg16_names[8]
+ static const HChar* ireg16_names[8]
= { "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di" };
- static HChar* ireg8_names[8]
+ static const HChar* ireg8_names[8]
= { "%al", "%cl", "%dl", "%bl",
"%ah{sp}", "%ch{bp}", "%dh{si}", "%bh{di}" };
if (reg < 0 || reg > 7) goto bad;
@@ -1287,7 +1287,7 @@
return NULL; /*notreached*/
}
-static HChar* nameSReg ( UInt sreg )
+static const HChar* nameSReg ( UInt sreg )
{
switch (sreg) {
case R_ES: return "%es";
@@ -1300,24 +1300,24 @@
}
}
-static HChar* nameMMXReg ( Int mmxreg )
+static const HChar* nameMMXReg ( Int mmxreg )
{
- static HChar* mmx_names[8]
+ static const HChar* mmx_names[8]
= { "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7" };
if (mmxreg < 0 || mmxreg > 7) vpanic("nameMMXReg(x86,guest)");
return mmx_names[mmxreg];
}
-static HChar* nameXMMReg ( Int xmmreg )
+static const HChar* nameXMMReg ( Int xmmreg )
{
- static HChar* xmm_names[8]
+ static const HChar* xmm_names[8]
= { "%xmm0", "%xmm1", "%xmm2", "%xmm3",
"%xmm4", "%xmm5", "%xmm6", "%xmm7" };
if (xmmreg < 0 || xmmreg > 7) vpanic("name_of_xmm_reg");
return xmm_names[xmmreg];
}
-static HChar* nameMMXGran ( Int gran )
+static const HChar* nameMMXGran ( Int gran )
{
switch (gran) {
case 0: return "b";
@@ -1401,7 +1401,7 @@
/*------------------------------------------------------------*/
static
-HChar* sorbTxt ( UChar sorb )
+const HChar* sorbTxt ( UChar sorb )
{
switch (sorb) {
case 0: return ""; /* no override */
@@ -1827,7 +1827,7 @@
Bool keep,
Int size,
Int delta0,
- HChar* t_x86opc )
+ const HChar* t_x86opc )
{
HChar dis_buf[50];
Int len;
@@ -1940,7 +1940,7 @@
Bool keep,
Int size,
Int delta0,
- HChar* t_x86opc )
+ const HChar* t_x86opc )
{
HChar dis_buf[50];
Int len;
@@ -2143,7 +2143,7 @@
IROp op8,
Bool keep,
Int delta,
- HChar* t_x86opc )
+ const HChar* t_x86opc )
{
IRType ty = szToITy(size);
IRTemp dst0 = newTemp(ty);
@@ -2389,7 +2389,7 @@
UInt dis_Grp2 ( UChar sorb,
Int delta, UChar modrm,
Int am_sz, Int d_sz, Int sz, IRExpr* shift_expr,
- HChar* shift_expr_txt, Bool* decode_OK )
+ const HChar* shift_expr_txt, Bool* decode_OK )
{
/* delta on entry points at the modrm byte. */
HChar dis_buf[50];
@@ -2737,7 +2737,7 @@
EDX:EAX/DX:AX/AX.
*/
static void codegen_mulL_A_D ( Int sz, Bool syned,
- IRTemp tmp, HChar* tmp_txt )
+ IRTemp tmp, const HChar* tmp_txt )
{
IRType ty = szToITy(sz);
IRTemp t1 = newTemp(ty);
@@ -3180,7 +3180,7 @@
static
void dis_string_op( void (*dis_OP)( Int, IRTemp ),
- Int sz, HChar* name, UChar sorb )
+ Int sz, const HChar* name, UChar sorb )
{
IRTemp t_inc = newTemp(Ity_I32);
vassert(sorb == 0); /* hmm. so what was the point of passing it in? */
@@ -3279,7 +3279,7 @@
void dis_REP_op ( /*MOD*/DisResult* dres,
X86Condcode cond,
void (*dis_OP)(Int, IRTemp),
- Int sz, Addr32 eip, Addr32 eip_next, HChar* name )
+ Int sz, Addr32 eip, Addr32 eip_next, const HChar* name )
{
IRTemp t_inc = newTemp(Ity_I32);
IRTemp tc = newTemp(Ity_I32); /* ECX */
@@ -3644,7 +3644,7 @@
Need to check ST(0)'s tag on read, but not on write.
*/
static
-void fp_do_op_mem_ST_0 ( IRTemp addr, HChar* op_txt, HChar* dis_buf,
+void fp_do_op_mem_ST_0 ( IRTemp addr, const HChar* op_txt, HChar* dis_buf,
IROp op, Bool dbl )
{
DIP("f%s%c %s\n", op_txt, dbl?'l':'s', dis_buf);
@@ -3670,7 +3670,7 @@
Need to check ST(0)'s tag on read, but not on write.
*/
static
-void fp_do_oprev_mem_ST_0 ( IRTemp addr, HChar* op_txt, HChar* dis_buf,
+void fp_do_oprev_mem_ST_0 ( IRTemp addr, const HChar* op_txt, HChar* dis_buf,
IROp op, Bool dbl )
{
DIP("f%s%c %s\n", op_txt, dbl?'l':'s', dis_buf);
@@ -3696,7 +3696,7 @@
Check dst and src tags when reading but not on write.
*/
static
-void fp_do_op_ST_ST ( HChar* op_txt, IROp op, UInt st_src, UInt st_dst,
+void fp_do_op_ST_ST ( const HChar* op_txt, IROp op, UInt st_src, UInt st_dst,
Bool pop_after )
{
DIP("f%s%s st(%d), st(%d)\n", op_txt, pop_after?"p":"",
@@ -3716,8 +3716,8 @@
Check dst and src tags when reading but not on write.
*/
static
-void fp_do_oprev_ST_ST ( HChar* op_txt, IROp op, UInt st_src, UInt st_dst,
- Bool pop_after )
+void fp_do_oprev_ST_ST ( const HChar* op_txt, IROp op, UInt st_src,
+ UInt st_dst, Bool pop_after )
{
DIP("f%s%s st(%d), st(%d)\n", op_txt, pop_after?"p":"",
(Int)st_src, (Int)st_dst );
@@ -5451,7 +5451,7 @@
UInt dis_MMXop_regmem_to_reg ( UChar sorb,
Int delta,
UChar opc,
- HChar* name,
+ const HChar* name,
Bool show_granularity )
{
HChar dis_buf[50];
@@ -5466,8 +5466,8 @@
Bool invG = False;
IROp op = Iop_INVALID;
void* hAddr = NULL;
- HChar* hName = NULL;
Bool eLeft = False;
+ const HChar* hName = NULL;
# define XXX(_name) do { hAddr = &_name; hName = #_name; } while (0)
@@ -5598,7 +5598,7 @@
of E. This is a straight copy of dis_SSE_shiftG_byE. */
static UInt dis_MMX_shiftG_byE ( UChar sorb, Int delta,
- HChar* opname, IROp op )
+ const HChar* opname, IROp op )
{
HChar dis_buf[50];
Int alen, size;
@@ -5674,7 +5674,7 @@
straight copy of dis_SSE_shiftE_imm. */
static
-UInt dis_MMX_shiftE_imm ( Int delta, HChar* opname, IROp op )
+UInt dis_MMX_shiftE_imm ( Int delta, const HChar* opname, IROp op )
{
Bool shl, shr, sar;
UChar rm = getIByte(delta);
@@ -6077,7 +6077,7 @@
Int sz,
IRExpr* shift_amt,
Bool amt_is_literal,
- HChar* shift_amt_txt,
+ const HChar* shift_amt_txt,
Bool left_shift )
{
/* shift_amt :: Ity_I8 is the amount to shift. shift_amt_txt is used
@@ -6194,7 +6194,7 @@
typedef enum { BtOpNone, BtOpSet, BtOpReset, BtOpComp } BtOp;
-static HChar* nameBtOp ( BtOp op )
+static const HChar* nameBtOp ( BtOp op )
{
switch (op) {
case BtOpNone: return "";
@@ -6870,7 +6870,7 @@
static UInt dis_SSE_E_to_G_all_wrk (
UChar sorb, Int delta,
- HChar* opname, IROp op,
+ const HChar* opname, IROp op,
Bool invertG
)
{
@@ -6905,7 +6905,7 @@
/* All lanes SSE binary operation, G = G `op` E. */
static
-UInt dis_SSE_E_to_G_all ( UChar sorb, Int delta, HChar* opname, IROp op )
+UInt dis_SSE_E_to_G_all ( UChar sorb, Int delta, const HChar* opname, IROp op )
{
return dis_SSE_E_to_G_all_wrk( sorb, delta, opname, op, False );
}
@@ -6914,7 +6914,7 @@
static
UInt dis_SSE_E_to_G_all_invG ( UChar sorb, Int delta,
- HChar* opname, IROp op )
+ const HChar* opname, IROp op )
{
return dis_SSE_E_to_G_all_wrk( sorb, delta, opname, op, True );
}
@@ -6923,7 +6923,7 @@
/* Lowest 32-bit lane only SSE binary operation, G = G `op` E. */
static UInt dis_SSE_E_to_G_lo32 ( UChar sorb, Int delta,
- HChar* opname, IROp op )
+ const HChar* opname, IROp op )
{
HChar dis_buf[50];
Int alen;
@@ -6958,7 +6958,7 @@
/* Lower 64-bit lane only SSE binary operation, G = G `op` E. */
static UInt dis_SSE_E_to_G_lo64 ( UChar sorb, Int delta,
- HChar* opname, IROp op )
+ const HChar* opname, IROp op )
{
HChar dis_buf[50];
Int alen;
@@ -6994,7 +6994,7 @@
static UInt dis_SSE_E_to_G_unary_all (
UChar sorb, Int delta,
- HChar* opname, IROp op
+ const HChar* opname, IROp op
)
{
HChar dis_buf[50];
@@ -7024,7 +7024,7 @@
static UInt dis_SSE_E_to_G_unary_lo32 (
UChar sorb, Int delta,
- HChar* opname, IROp op
+ const HChar* opname, IROp op
)
{
/* First we need to get the old G value and patch the low 32 bits
@@ -7067,7 +7067,7 @@
static UInt dis_SSE_E_to_G_unary_lo64 (
UChar sorb, Int delta,
- HChar* opname, IROp op
+ const HChar* opname, IROp op
)
{
/* First we need to get the old G value and patch the low 64 bits
@@ -7112,7 +7112,7 @@
*/
static UInt dis_SSEint_E_to_G(
UChar sorb, Int delta,
- HChar* opname, IROp op,
+ const HChar* opname, IROp op,
Bool eLeft
)
{
@@ -7198,7 +7198,7 @@
/* Handles SSE 32F/64F comparisons. */
static UInt dis_SSEcmp_E_to_G ( UChar sorb, Int delta,
- HChar* opname, Bool all_lanes, Int sz )
+ const HChar* opname, Bool all_lanes, Int sz )
{
HChar dis_buf[50];
Int alen, imm8;
@@ -7261,7 +7261,7 @@
of E. */
static UInt dis_SSE_shiftG_byE ( UChar sorb, Int delta,
- HChar* opname, IROp op )
+ const HChar* opname, IROp op )
{
HChar dis_buf[50];
Int alen, size;
@@ -7335,7 +7335,7 @@
/* Vector by scalar shift of E by an immediate byte. */
static
-UInt dis_SSE_shiftE_imm ( Int delta, HChar* opname, IROp op )
+UInt dis_SSE_shiftE_imm ( Int delta, const HChar* opname, IROp op )
{
Bool shl, shr, sar;
UChar rm = getIByte(delta);
@@ -9091,7 +9091,7 @@
if (insn[0] == 0x0F && insn[1] == 0x18
&& !epartIsReg(insn[2])
&& gregOfRM(insn[2]) >= 0 && gregOfRM(insn[2]) <= 3) {
- HChar* hintstr = "??";
+ const HChar* hintstr = "??";
modrm = getIByte(delta+2);
vassert(!epartIsReg(modrm));
@@ -9116,7 +9116,7 @@
if (insn[0] == 0x0F && insn[1] == 0x0D
&& !epartIsReg(insn[2])
&& gregOfRM(insn[2]) >= 0 && gregOfRM(insn[2]) <= 1) {
- HChar* hintstr = "??";
+ const HChar* hintstr = "??";
modrm = getIByte(delta+2);
vassert(!epartIsReg(modrm));
@@ -10043,8 +10043,8 @@
/* 66 0F 6F = MOVDQA -- move from E (mem or xmm) to G (xmm). */
if (sz == 2 && insn[0] == 0x0F
&& (insn[1] == 0x28 || insn[1] == 0x10 || insn[1] == 0x6F)) {
- HChar* wot = insn[1]==0x28 ? "apd" :
- insn[1]==0x10 ? "upd" : "dqa";
+ const HChar* wot = insn[1]==0x28 ? "apd" :
+ insn[1]==0x10 ? "upd" : "dqa";
modrm = getIByte(delta+2);
if (epartIsReg(modrm)) {
putXMMReg( gregOfRM(modrm),
@@ -10069,7 +10069,7 @@
/* 66 0F 11 = MOVUPD -- move from G (xmm) to E (mem or xmm). */
if (sz == 2 && insn[0] == 0x0F
&& (insn[1] == 0x29 || insn[1] == 0x11)) {
- HChar* wot = insn[1]==0x29 ? "apd" : "upd";
+ const HChar* wot = insn[1]==0x29 ? "apd" : "upd";
modrm = getIByte(delta+2);
if (epartIsReg(modrm)) {
/* fall through; awaiting test case */
@@ -11774,7 +11774,7 @@
IRTemp leftV = newTemp(Ity_V128);
IRTemp rightV = newTemp(Ity_V128);
Bool isAdd = insn[2] == 0x7C;
- HChar* str = isAdd ? "add" : "sub";
+ const HChar* str = isAdd ? "add" : "sub";
e3 = e2 = e1 = e0 = g3 = g2 = g1 = g0 = IRTemp_INVALID;
modrm = insn[3];
@@ -11817,7 +11817,7 @@
IRTemp leftV = newTemp(Ity_V128);
IRTemp rightV = newTemp(Ity_V128);
Bool isAdd = insn[1] == 0x7C;
- HChar* str = isAdd ? "add" : "sub";
+ const HChar* str = isAdd ? "add" : "sub";
modrm = insn[2];
if (epartIsReg(modrm)) {
@@ -11995,7 +11995,7 @@
&& insn[0] == 0x0F && insn[1] == 0x38
&& (insn[2] == 0x03 || insn[2] == 0x07 || insn[2] == 0x01
|| insn[2] == 0x05 || insn[2] == 0x02 || insn[2] == 0x06)) {
- HChar* str = "???";
+ const HChar* str = "???";
IROp opV64 = Iop_INVALID;
IROp opCatO = Iop_CatOddLanes16x4;
IROp opCatE = Iop_CatEvenLanes16x4;
@@ -12061,7 +12061,7 @@
&& insn[0] == 0x0F && insn[1] == 0x38
&& (insn[2] == 0x03 || insn[2] == 0x07 || insn[2] == 0x01
|| insn[2] == 0x05 || insn[2] == 0x02 || insn[2] == 0x06)) {
- HChar* str = "???";
+ const HChar* str = "???";
IROp opV64 = Iop_INVALID;
IROp opCatO = Iop_CatOddLanes16x4;
IROp opCatE = Iop_CatEvenLanes16x4;
@@ -12210,7 +12210,7 @@
&& (insn[2] == 0x08 || insn[2] == 0x09 || insn[2] == 0x0A)) {
IRTemp sV = newTemp(Ity_I64);
IRTemp dV = newTemp(Ity_I64);
- HChar* str = "???";
+ const HChar* str = "???";
Int laneszB = 0;
switch (insn[2]) {
@@ -12256,7 +12256,7 @@
IRTemp sLo = newTemp(Ity_I64);
IRTemp dHi = newTemp(Ity_I64);
IRTemp dLo = newTemp(Ity_I64);
- HChar* str = "???";
+ const HChar* str = "???";
Int laneszB = 0;
switch (insn[2]) {
@@ -12305,7 +12305,7 @@
&& insn[0] == 0x0F && insn[1] == 0x38
&& (insn[2] == 0x1C || insn[2] == 0x1D || insn[2] == 0x1E)) {
IRTemp sV = newTemp(Ity_I64);
- HChar* str = "???";
+ const HChar* str = "???";
Int laneszB = 0;
switch (insn[2]) {
@@ -12347,7 +12347,7 @@
IRTemp sV = newTemp(Ity_V128);
IRTemp sHi = newTemp(Ity_I64);
IRTemp sLo = newTemp(Ity_I64);
- HChar* str = "???";
+ const HChar* str = "???";
Int laneszB = 0;
switch (insn[2]) {
@@ -13277,7 +13277,7 @@
case 0x7E: /* JLEb/JNGb (jump less or equal) */
case 0x7F: /* JGb/JNLEb (jump greater) */
{ Int jmpDelta;
- HChar* comment = "";
+ const HChar* comment = "";
jmpDelta = (Int)getSDisp8(delta);
vassert(-128 <= jmpDelta && jmpDelta < 128);
d32 = (((Addr32)guest_EIP_bbstart)+delta+1) + jmpDelta;
@@ -13356,7 +13356,7 @@
IRExpr* zbit = NULL;
IRExpr* count = NULL;
IRExpr* cond = NULL;
- HChar* xtra = NULL;
+ const HChar* xtra = NULL;
if (sz != 4) goto decode_failure;
d32 = (((Addr32)guest_EIP_bbstart)+delta+1) + getSDisp8(delta);
@@ -14673,8 +14673,8 @@
declared to mod eax, wr ebx, ecx, edx
*/
IRDirty* d = NULL;
- HChar* fName = NULL;
void* fAddr = NULL;
+ const HChar* fName = NULL;
if (archinfo->hwcaps & VEX_HWCAPS_X86_SSE2) {
fName = "x86g_dirtyhelper_CPUID_sse2";
fAddr = &x86g_dirtyhelper_CPUID_sse2;
@@ -14837,7 +14837,7 @@
case 0x8E: /* JLEb/JNGb (jump less or equal) */
case 0x8F: /* JGb/JNLEb (jump greater) */
{ Int jmpDelta;
- HChar* comment = "";
+ const HChar* comment = "";
jmpDelta = (Int)getUDisp32(delta);
d32 = (((Addr32)guest_EIP_bbstart)+delta+4) + jmpDelta;
delta += 4;
Modified: trunk/priv/main_util.c (+3 -3)
===================================================================
--- trunk/priv/main_util.c 2012-11-20 17:32:48 +00:00 (rev 2563)
+++ trunk/priv/main_util.c 2012-11-21 00:36:55 +00:00 (rev 2564)
@@ -158,7 +158,7 @@
__attribute__((noreturn))
void private_LibVEX_alloc_OOM(void)
{
- HChar* pool = "???";
+ const HChar* pool = "???";
if (private_LibVEX_alloc_first == &temporary[0]) pool = "TEMP";
if (private_LibVEX_alloc_first == &permanent[0]) pool = "PERM";
vex_printf("VEX temporary storage exhausted.\n");
@@ -328,7 +328,7 @@
while (0)
# define PUTSTR(_str) \
- do { HChar* _qq = _str; for (; *_qq; _qq++) PUT(*_qq); } \
+ do { const HChar* _qq = _str; for (; *_qq; _qq++) PUT(*_qq); } \
while (0)
const HChar* saved_format;
@@ -380,7 +380,7 @@
switch (*format) {
case 's': {
- HChar* str = va_arg(ap, HChar*);
+ const HChar* str = va_arg(ap, HChar*);
if (str == NULL)
str = "(null)";
len1 = len3 = 0;
Modified: trunk/priv/main_main.c (+10 -10)
===================================================================
--- trunk/priv/main_main.c 2012-11-20 17:32:48 +00:00 (rev 2563)
+++ trunk/priv/main_main.c 2012-11-21 00:36:55 +00:00 (rev 2564)
@@ -71,7 +71,7 @@
/* --------- fwds ... --------- */
static Bool are_valid_hwcaps ( VexArch arch, UInt hwcaps );
-static HChar* show_hwcaps ( VexArch arch, UInt hwcaps );
+static const HChar* show_hwcaps ( VexArch arch, UInt hwcaps );
/* --------- Initialise the library. --------- */
@@ -1070,7 +1070,7 @@
const HChar* LibVEX_ppVexHwCaps ( VexArch arch, UInt hwcaps )
{
- HChar* str = show_hwcaps(arch,hwcaps);
+ const HChar* str = show_hwcaps(arch,hwcaps);
return str ? str : "INVALID";
}
@@ -1107,7 +1107,7 @@
be NULL for invalid combinations of flags, so these functions also
serve as a way to validate hwcaps values. */
-static HChar* show_hwcaps_x86 ( UInt hwcaps )
+static const HChar* show_hwcaps_x86 ( UInt hwcaps )
{
/* Monotonic, SSE3 > SSE2 > SSE1 > baseline. */
switch (hwcaps) {
@@ -1131,7 +1131,7 @@
}
}
-static HChar* show_hwcaps_amd64 ( UInt hwcaps )
+static const HChar* show_hwcaps_amd64 ( UInt hwcaps )
{
/* SSE3 and CX16 are orthogonal and > baseline, although we really
don't expect to come across anything which can do SSE3 but can't
@@ -1169,7 +1169,7 @@
}
}
-static HChar* show_hwcaps_ppc32 ( UInt hwcaps )
+static const HChar* show_hwcaps_ppc32 ( UInt hwcaps )
{
/* Monotonic with complications. Basically V > F > baseline,
but once you have F then you can have FX or GX too. */
@@ -1194,7 +1194,7 @@
return NULL;
}
-static HChar* show_hwcaps_ppc64 ( UInt hwcaps )
+static const HChar* show_hwcaps_ppc64 ( UInt hwcaps )
{
/* Monotonic with complications. Basically V > baseline(==F),
but once you have F then you can have FX or GX too. */
@@ -1217,7 +1217,7 @@
return NULL;
}
-static HChar* show_hwcaps_arm ( UInt hwcaps )
+static const HChar* show_hwcaps_arm ( UInt hwcaps )
{
Bool N = ((hwcaps & VEX_HWCAPS_ARM_NEON) != 0);
Bool vfp = ((hwcaps & (VEX_HWCAPS_ARM_VFP |
@@ -1257,7 +1257,7 @@
return NULL;
}
-static HChar* show_hwcaps_s390x ( UInt hwcaps )
+static const HChar* show_hwcaps_s390x ( UInt hwcaps )
{
static const HChar prefix[] = "s390x";
static const HChar facilities[][6] = {
@@ -1308,7 +1308,7 @@
return buf;
}
-static HChar* show_hwcaps_mips32 ( UInt hwcaps )
+static const HChar* show_hwcaps_mips32 ( UInt hwcaps )
{
if (hwcaps == 0x00010000) return "MIPS-baseline";
if (hwcaps == 0x00020000) return "Broadcom-baseline";
@@ -1316,7 +1316,7 @@
}
/* ---- */
-static HChar* show_hwcaps ( VexArch arch, UInt hwcaps )
+static const HChar* show_hwcaps ( VexArch arch, UInt hwcaps )
{
switch (arch) {
case VexArchX86: return show_hwcaps_x86(hwcaps);
Modified: trunk/priv/host_ppc_defs.h (+10 -10)
===================================================================
--- trunk/priv/host_ppc_defs.h 2012-11-20 17:32:48 +00:00 (rev 2563)
+++ trunk/priv/host_ppc_defs.h 2012-11-21 00:36:55 +00:00 (rev 2564)
@@ -186,7 +186,7 @@
}
PPCCondCode;
-extern HChar* showPPCCondCode ( PPCCondCode );
+extern const HChar* showPPCCondCode ( PPCCondCode );
/* constructor */
extern PPCCondCode mk_PPCCondCode ( PPCCondTest, PPCCondFlag );
@@ -326,7 +326,7 @@
}
PPCUnaryOp;
-extern HChar* showPPCUnaryOp ( PPCUnaryOp );
+extern const HChar* showPPCUnaryOp ( PPCUnaryOp );
/* --------- */
@@ -339,8 +339,8 @@
PPCAluOp;
extern
-HChar* showPPCAluOp ( PPCAluOp,
- Bool /* is the 2nd operand an immediate? */);
+const HChar* showPPCAluOp ( PPCAluOp,
+ Bool /* is the 2nd operand an immediate? */);
/* --------- */
@@ -352,9 +352,9 @@
PPCShftOp;
extern
-HChar* showPPCShftOp ( PPCShftOp,
- Bool /* is the 2nd operand an immediate? */,
- Bool /* is this a 32bit or 64bit op? */ );
+const HChar* showPPCShftOp ( PPCShftOp,
+ Bool /* is the 2nd operand an immediate? */,
+ Bool /* is this a 32bit or 64bit op? */ );
/* --------- */
@@ -386,7 +386,7 @@
}
PPCFpOp;
-extern HChar* showPPCFpOp ( PPCFpOp );
+extern const HChar* showPPCFpOp ( PPCFpOp );
/* --------- */
@@ -425,7 +425,7 @@
}
PPCAvOp;
-extern HChar* showPPCAvOp ( PPCAvOp );
+extern const HChar* showPPCAvOp ( PPCAvOp );
/* --------- */
@@ -445,7 +445,7 @@
}
PPCAvFpOp;
-extern HChar* showPPCAvFpOp ( PPCAvFpOp );
+extern const HChar* showPPCAvFpOp ( PPCAvFpOp );
/* --------- */
Modified: trunk/priv/host_ppc_defs.c (+10 -10)
===================================================================
--- trunk/priv/host_ppc_defs.c 2012-11-20 17:32:48 +00:00 (rev 2563)
+++ trunk/priv/host_ppc_defs.c 2012-11-21 00:36:55 +00:00 (rev 2564)
@@ -47,7 +47,7 @@
void ppHRegPPC ( HReg reg )
{
Int r;
- static HChar* ireg32_names[32]
+ static const HChar* ireg32_names[32]
= { "%r0", "%r1", "%r2", "%r3",
"%r4", "%r5", "%r6", "%r7",
"%r8", "%r9", "%r10", "%r11",
@@ -273,7 +273,7 @@
/* --------- Condition codes, Intel encoding. --------- */
-HChar* showPPCCondCode ( PPCCondCode cond )
+const HChar* showPPCCondCode ( PPCCondCode cond )
{
if (cond.test == Pct_ALWAYS) return "always";
@@ -572,7 +572,7 @@
/* --------- Instructions. --------- */
-HChar* showPPCUnaryOp ( PPCUnaryOp op ) {
+const HChar* showPPCUnaryOp ( PPCUnaryOp op ) {
switch (op) {
case Pun_NOT: return "not";
case Pun_NEG: return "neg";
@@ -583,7 +583,7 @@
}
}
-HChar* showPPCAluOp ( PPCAluOp op, Bool immR ) {
+const HChar* showPPCAluOp ( PPCAluOp op, Bool immR ) {
switch (op) {
case Palu_ADD: return immR ? "addi" : "add";
case Palu_SUB: return immR ? "subi" : "sub";
@@ -594,7 +594,7 @@
}
}
-HChar* showPPCShftOp ( PPCShftOp op, Bool immR, Bool sz32 ) {
+const HChar* showPPCShftOp ( PPCShftOp op, Bool immR, Bool sz32 ) {
switch (op) {
case Pshft_SHL: return sz32 ? (immR ? "slwi" : "slw") :
(immR ? "sldi" : "sld");
@@ -606,7 +606,7 @@
}
}
-HChar* showPPCFpOp ( PPCFpOp op ) {
+const HChar* showPPCFpOp ( PPCFpOp op ) {
switch (op) {
case Pfp_ADDD: return "fadd";
case Pfp_SUBD: return "fsub";
@@ -655,7 +655,7 @@
}
}
-HChar* showPPCAvOp ( PPCAvOp op ) {
+const HChar* showPPCAvOp ( PPCAvOp op ) {
switch (op) {
/* Unary */
@@ -722,7 +722,7 @@
}
}
-HChar* showPPCAvFpOp ( PPCAvFpOp op ) {
+const HChar* showPPCAvFpOp ( PPCAvFpOp op ) {
switch (op) {
/* Floating Point Binary */
case Pavfp_ADDF: return "vaddfp";
@@ -1742,7 +1742,7 @@
ppHRegPPC(i->Pin.FpRSP.src);
return;
case Pin_FpCftI: {
- HChar* str = "fc?????";
+ const HChar* str = "fc?????";
/* Note that "fcfids" is missing from below. That instruction would
* satisfy the predicate:
* (i->Pin.FpCftI.fromI == True && i->Pin.FpCftI.int32 == False)
@@ -1820,7 +1820,7 @@
case Pin_AvLdSt: {
UChar sz = i->Pin.AvLdSt.sz;
- HChar* str_size;
+ const HChar* str_size;
if (i->Pin.AvLdSt.addr->tag == Pam_IR) {
ppLoadImm(hregPPC_GPR30(mode64),
i->Pin.AvLdSt.addr->Pam.RR.index, mode64);
Modified: trunk/priv/guest_arm_toIR.c (+27 -27)
===================================================================
--- trunk/priv/guest_arm_toIR.c 2012-11-20 17:32:48 +00:00 (rev 2563)
+++ trunk/priv/guest_arm_toIR.c 2012-11-21 00:36:55 +00:00 (rev 2564)
@@ -1054,7 +1054,7 @@
/*--- Helpers for flag handling and conditional insns ---*/
/*------------------------------------------------------------*/
-static HChar* name_ARMCondcode ( ARMCondcode cond )
+static const HChar* name_ARMCondcode ( ARMCondcode cond )
{
switch (cond) {
case ARMCondEQ: return "{eq}";
@@ -1077,7 +1077,7 @@
}
}
/* and a handy shorthand for it */
-static HChar* nCC ( ARMCondcode cond ) {
+static const HChar* nCC ( ARMCondcode cond ) {
return name_ARMCondcode(cond);
}
@@ -11051,7 +11051,7 @@
putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
}
- HChar* nm = bL==1 ? "ld" : "st";
+ const HChar* nm = bL==1 ? "ld" : "st";
switch (summary) {
case 1: DIP("f%smx%s r%u, {d%u-d%u}\n",
nm, nCC(conq), rN, dD, dD + nRegs - 1);
@@ -11188,7 +11188,7 @@
putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
}
- HChar* nm = bL==1 ? "ld" : "st";
+ const HChar* nm = bL==1 ? "ld" : "st";
switch (summary) {
case 1: DIP("f%smd%s r%u, {d%u-d%u}\n",
nm, nCC(conq), rN, dD, dD + nRegs - 1);
@@ -11937,7 +11937,7 @@
putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
}
- HChar* nm = bL==1 ? "ld" : "st";
+ const HChar* nm = bL==1 ? "ld" : "st";
switch (summary) {
case 1: DIP("f%sms%s r%u, {s%u-s%u}\n",
nm, nCC(conq), rN, fD, fD + nRegs - 1);
@@ -12735,7 +12735,7 @@
IRTemp res = IRTemp_INVALID;
IRTemp oldV = IRTemp_INVALID;
IRTemp oldC = IRTemp_INVALID;
- HChar* name = NULL;
+ const HChar* name = NULL;
IROp op = Iop_INVALID;
Bool ok;
@@ -13369,7 +13369,7 @@
shalf load H 1 L 1 S 1
sbyte load H 0 L 1 S 1
*/
- HChar* name = NULL;
+ const HChar* name = NULL;
/* generate the transfer */
/**/ if (bH == 1 && bL == 0 && bS == 0) { // halfword store
storeLE( mkexpr(taT), unop(Iop_32to16, getIRegA(rD)) );
@@ -13520,7 +13520,7 @@
DIP("b%s 0x%x\n", link ? "l" : "", dst);
} else {
/* conditional transfer to 'dst' */
- HChar* comment = "";
+ const HChar* comment = "";
/* First see if we can do some speculative chasing into one
arm or the other. Be conservative and only chase if
@@ -13976,7 +13976,7 @@
UInt rN = INSN(19,16);
IRType ty = Ity_INVALID;
IROp widen = Iop_INVALID;
- HChar* nm = NULL;
+ const HChar* nm = NULL;
Bool valid = True;
switch (INSN(22,21)) {
case 0: nm = ""; ty = Ity_I32; break;
@@ -14031,7 +14031,7 @@
UInt rD = INSN(15,12);
IRType ty = Ity_INVALID;
IROp narrow = Iop_INVALID;
- HChar* nm = NULL;
+ const HChar* nm = NULL;
Bool valid = True;
switch (INSN(22,21)) {
case 0: nm = ""; ty = Ity_I32; break;
@@ -14131,7 +14131,7 @@
IRTemp srcT = newTemp(Ity_I32);
IRTemp rotT = newTemp(Ity_I32);
IRTemp dstT = newTemp(Ity_I32);
- HChar* nm = "???";
+ const HChar* nm = "???";
assign(srcT, getIRegA(rM));
assign(rotT, genROR32(srcT, 8 * rot)); /* 0, 8, 16 or 24 only */
switch (subopc) {
@@ -14398,7 +14398,7 @@
/* doubleword store S 1
doubleword load S 0
*/
- HChar* name = NULL;
+ const HChar* name = NULL;
/* generate the transfers */
if (bS == 1) { // doubleword store
storeLE( binop(Iop_Add32, mkexpr(taT), mkU32(0)), getIRegA(rD+0) );
@@ -15221,7 +15221,7 @@
test for this case for every condition code update. */
IROp anOp = Iop_INVALID;
- HChar* anOpNm = NULL;
+ const HChar* anOpNm = NULL;
/* ================ 16-bit 15:6 cases ================ */
@@ -15457,7 +15457,7 @@
IRTemp rSt = newTemp(Ity_I32);
IRTemp res = newTemp(Ity_I32);
IRTemp resC = newTemp(Ity_I32);
- HChar* wot = "???";
+ const HChar* wot = "???";
assign(rSt, getIRegT(rS));
assign(rDt, getIRegT(rD));
assign(oldV, mk_armg_calculate_flag_v());
@@ -16403,7 +16403,7 @@
IRTemp resC = newTemp(Ity_I32);
IRTemp rMt = newTemp(Ity_I32);
IRTemp oldV = newTemp(Ity_I32);
- HChar* wot = "???";
+ const HChar* wot = "???";
assign(rMt, getIRegT(rM));
assign(oldV, mk_armg_calculate_flag_v());
/* Looks like INSN0(12,11) are the standard 'how' encoding.
@@ -16838,7 +16838,7 @@
assign(argL, getIRegT(rN));
assign(argR, mkU32(imm32));
assign(oldC, mk_armg_calculate_flag_c() );
- HChar* nm = "???";
+ const HChar* nm = "???";
switch (INSN0(9,5)) {
case BITS5(0,1,0,1,0): // ADC
nm = "adc";
@@ -16888,7 +16888,7 @@
if (!isBadRegT(rN) && !isBadRegT(rD)) {
Bool notArgR = False;
IROp op = Iop_INVALID;
- HChar* nm = "???";
+ const HChar* nm = "???";
switch (INSN0(9,5)) {
case BITS5(0,0,0,1,0): op = Iop_Or32; nm = "orr"; break;
case BITS5(0,0,0,0,0): op = Iop_And32; nm = "and"; break;
@@ -16955,7 +16955,7 @@
if (valid) {
Bool swap = False;
IROp op = Iop_INVALID;
- HChar* nm = "???";
+ const HChar* nm = "???";
switch (INSN0(8,5)) {
case BITS4(1,0,0,0): op = Iop_Add32; nm = "add"; break;
case BITS4(1,1,0,1): op = Iop_Sub32; nm = "sub"; break;
@@ -17033,7 +17033,7 @@
dis_buf, &argR, NULL, rMt, how, imm5, rM
);
- HChar* nm = "???";
+ const HChar* nm = "???";
IRTemp res = newTemp(Ity_I32);
switch (INSN0(8,5)) {
case BITS4(1,0,1,0): // ADC
@@ -17086,7 +17086,7 @@
if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
Bool notArgR = False;
IROp op = Iop_INVALID;
- HChar* nm = "???";
+ const HChar* nm = "???";
switch (INSN0(8,5)) {
case BITS4(0,0,0,0): op = Iop_And32; nm = "and"; break;
case BITS4(0,0,1,0): op = Iop_Or32; nm = "orr"; break;
@@ -17156,8 +17156,8 @@
IRTemp res = newTemp(Ity_I32);
IRTemp oldC = bS ? newTemp(Ity_I32) : IRTemp_INVALID;
IRTemp oldV = bS ? newTemp(Ity_I32) : IRTemp_INVALID;
- HChar* nms[4] = { "lsl", "lsr", "asr", "ror" };
- HChar* nm = nms[how];
+ const HChar* nms[4] = { "lsl", "lsr", "asr", "ror" };
+ const HChar* nm = nms[how];
assign(rNt, getIRegT(rN));
assign(rMt, getIRegT(rM));
compute_result_and_C_after_shift_by_reg(
@@ -17367,7 +17367,7 @@
Bool syned = False;
Bool isST = False;
IRType ty = Ity_I8;
- HChar* nm = "???";
+ const HChar* nm = "???";
switch (INSN0(8,4)) {
case BITS5(0,0,0,0,0): // strb
@@ -17551,7 +17551,7 @@
Bool syned = False;
Bool isST = False;
IRType ty = Ity_I8;
- HChar* nm = "???";
+ const HChar* nm = "???";
switch (INSN0(8,4)) {
case BITS5(0,0,0,0,0): // strb
@@ -17688,7 +17688,7 @@
Bool syned = False;
Bool isST = False;
IRType ty = Ity_I8;
- HChar* nm = "???";
+ const HChar* nm = "???";
switch (INSN0(8,4)) {
case BITS5(0,1,0,0,0): // strb
@@ -17875,7 +17875,7 @@
putIRegT(rN, mkexpr(postAddr), IRTemp_INVALID);
}
- HChar* nm = bL ? "ldrd" : "strd";
+ const HChar* nm = bL ? "ldrd" : "strd";
if (bP == 1 && bW == 0) {
DIP("%s.w r%u, r%u, [r%u, #%c%u]\n",
@@ -18075,7 +18075,7 @@
UInt rM = INSN1(3,0);
UInt rot = INSN1(5,4);
if (!isBadRegT(rD) && !isBadRegT(rM)) {
- HChar* nm = "???";
+ const HChar* nm = "???";
IRTemp srcT = newTemp(Ity_I32);
IRTemp rotT = newTemp(Ity_I32);
IRTemp dstT = newTemp(Ity_I32);
Modified: trunk/priv/guest_ppc_toIR.c (+11 -10)
===================================================================
--- trunk/priv/guest_ppc_toIR.c 2012-11-20 17:32:48 +00:00 (rev 2563)
+++ trunk/priv/guest_ppc_toIR.c 2012-11-21 00:36:55 +00:00 (rev 2564)
@@ -1553,7 +1553,7 @@
the address of the next instruction to be executed.
*/
static void make_redzone_AbiHint ( VexAbiInfo* vbi,
- IRTemp nia, HChar* who )
+ IRTemp nia, const HChar* who )
{
Int szB = vbi->guest_stack_redzone_size;
if (0) vex_printf("AbiHint: %s\n", who);
@@ -12089,7 +12089,7 @@
case 0x1A0: // xvsubdp (VSX Vector Subtract Double-Precision)
{
IROp mOp;
- HChar * oper_name;
+ const HChar * oper_name;
switch (opc2) {
case 0x1E0:
mOp = Iop_DivF64;
@@ -12158,7 +12158,7 @@
*/
Bool negate;
IROp mOp = Iop_INVALID;
- HChar * oper_name = NULL;
+ const HChar * oper_name = NULL;
Bool mdp = False;
switch (opc2) {
@@ -12420,7 +12420,7 @@
IRTemp t3, t2, t1, t0;
Bool msp = False;
Bool negate;
- HChar * oper_name = NULL;
+ const HChar * oper_name = NULL;
IROp mOp = Iop_INVALID;
switch (opc2) {
case 0x104: case 0x124:
@@ -12811,7 +12811,8 @@
/*
* Helper function for vector/scalar double precision fp round to integer instructions.
*/
-static IRExpr * _do_vsx_fp_roundToInt(IRTemp frB_I64, UInt opc2, HChar * insn_suffix)
+static IRExpr * _do_vsx_fp_roundToInt(IRTemp frB_I64, UInt opc2,
+ const HChar * insn_suffix)
{
/* The same rules apply for x{s|v}rdpi{m|p|c|z} as for floating point round operations (fri{m|n|p|z}). */
@@ -13271,7 +13272,7 @@
IRTemp frBLo_I64 = newTemp(Ity_I64);
IRExpr * frD_fp_roundHi = NULL;
IRExpr * frD_fp_roundLo = NULL;
- HChar * insn_suffix = NULL;
+ const HChar * insn_suffix = NULL;
assign( frBHi_I64, unop( Iop_V128HIto64, getVSReg( XB ) ) );
frD_fp_roundHi = _do_vsx_fp_roundToInt(frBHi_I64, opc2, insn_suffix);
@@ -13291,7 +13292,7 @@
case 0x152: // xvrspip (VSX Vector Round to SinglePrecision Integer using round toward +Infinity)
case 0x132: // xvrspiz (VSX Vector Round to SinglePrecision Integer using round toward Zero)
{
- HChar * insn_suffix = NULL;
+ const HChar * insn_suffix = NULL;
IROp op;
if (opc2 != 0x156) {
// Use pre-defined IRop's for vrfi{m|n|p|z}
@@ -13880,7 +13881,7 @@
{
IRTemp frB_I64 = newTemp(Ity_I64);
IRExpr * frD_fp_round = NULL;
- HChar * insn_suffix = NULL;
+ const HChar * insn_suffix = NULL;
assign(frB_I64, unop(Iop_V128HIto64, mkexpr( vB )));
frD_fp_round = _do_vsx_fp_roundToInt(frB_I64, opc2, insn_suffix);
@@ -14218,7 +14219,7 @@
case 0x48: // xxmrghw (VSX Merge High Word)
case 0xc8: // xxmrglw (VSX Merge Low Word)
{
- HChar type = (opc2 == 0x48) ? 'h' : 'l';
+ const HChar type = (opc2 == 0x48) ? 'h' : 'l';
IROp word_op = (opc2 == 0x48) ? Iop_V128HIto64 : Iop_V128to64;
IRTemp a64 = newTemp(Ity_I64);
IRTemp ahi32 = newTemp(Ity_I32);
@@ -16273,7 +16274,7 @@
struct vsx_insn {
UInt opcode;
- HChar * name;
+ const HChar * name;
};
// ATTENTION: Keep this array sorted on the opcocde!!!
Modified: trunk/priv/host_s390_defs.c (+1 -1)
===================================================================
--- trunk/priv/host_s390_defs.c 2012-11-20 17:32:48 +00:00 (rev 2563)
+++ trunk/priv/host_s390_defs.c 2012-11-21 00:36:55 +00:00 (rev 2564)
@@ -5237,7 +5237,7 @@
/* Helper function for writing out a V insn */
static void
-s390_sprintf(HChar *buf, HChar *fmt, ...)
+s390_sprintf(HChar *buf, const HChar *fmt, ...)
{
HChar *p;
ULong value;
Modified: trunk/priv/guest_amd64_toIR.c (+127 -127)
===================================================================
--- trunk/priv/guest_amd64_toIR.c 2012-11-20 17:32:48 +00:00 (rev 2563)
+++ trunk/priv/guest_amd64_toIR.c 2012-11-21 00:36:55 +00:00 (rev 2564)
@@ -363,7 +363,7 @@
/* Bomb out if we can't handle something. */
__attribute__ ((noreturn))
-static void unimplemented ( HChar* str )
+static void unimplemented ( const HChar* str )
{
vex_printf("amd64toIR: unimplemented feature\n");
vpanic(str);
@@ -903,21 +903,21 @@
the case where sz==1 and no REX byte is present. */
static
-HChar* nameIReg ( Int sz, UInt reg, Bool irregular )
+const HChar* nameIReg ( Int sz, UInt reg, Bool irregular )
{
- static HChar* ireg64_names[16]
+ static const HChar* ireg64_names[16]
= { "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
"%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" };
- static HChar* ireg32_names[16]
+ static const HChar* ireg32_names[16]
= { "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
"%r8d", "%r9d", "%r10d","%r11d","%r12d","%r13d","%r14d","%r15d" };
- static HChar* ireg16_names[16]
+ static const HChar* ireg16_names[16]
= { "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
"%r8w", "%r9w", "%r10w","%r11w","%r12w","%r13w","%r14w","%r15w" };
- static HChar* ireg8_names[16]
+ static const HChar* ireg8_names[16]
= { "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
"%r8b", "%r9b", "%r10b","%r11b","%r12b","%r13b","%r14b","%r15b" };
- static HChar* ireg8_irregular[8]
+ static const HChar* ireg8_irregular[8]
= { "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh" };
vassert(reg < 16);
@@ -993,7 +993,7 @@
/* Read/write various widths of %RAX, as it has various
special-purpose uses. */
-static HChar* nameIRegRAX ( Int sz )
+static const HChar* nameIRegRAX ( Int sz )
{
switch (sz) {
case 1: return "%al";
@@ -1041,7 +1041,7 @@
/* Read/write various widths of %RDX, as it has various
special-purpose uses. */
-static HChar* nameIRegRDX ( Int sz )
+static const HChar* nameIRegRDX ( Int sz )
{
switch (sz) {
case 1: return "%dl";
@@ -1097,7 +1097,7 @@
stmt( IRStmt_Put( integerGuestReg64Offset(regno), e ) );
}
-static HChar* nameIReg64 ( UInt regno )
+static const HChar* nameIReg64 ( UInt regno )
{
return nameIReg( 8, regno, False );
}
@@ -1121,7 +1121,7 @@
unop(Iop_32Uto64,e) ) );
}
-static HChar* nameIReg32 ( UInt regno )
+static const HChar* nameIReg32 ( UInt regno )
{
return nameIReg( 4, regno, False );
}
@@ -1144,7 +1144,7 @@
unop(Iop_16Uto64,e) ) );
}
-static HChar* nameIReg16 ( UInt regno )
+static const HChar* nameIReg16 ( UInt regno )
{
return nameIReg( 2, regno, False );
}
@@ -1161,14 +1161,14 @@
return getIReg64( lo3bits | (getRexX(pfx) << 3) );
}
-static HChar* nameIReg64rexX ( Prefix pfx, UInt lo3bits )
+static const HChar* nameIReg64rexX ( Prefix pfx, UInt lo3bits )
{
vassert(lo3bits < 8);
vassert(IS_VALID_PFX(pfx));
return nameIReg( 8, lo3bits | (getRexX(pfx) << 3), False );
}
-static HChar* nameIRegRexB ( Int sz, Prefix pfx, UInt lo3bits )
+static const HChar* nameIRegRexB ( Int sz, Prefix pfx, UInt lo3bits )
{
vassert(lo3bits < 8);
vassert(IS_VALID_PFX(pfx));
@@ -1285,7 +1285,7 @@
}
static
-HChar* nameIRegG ( Int sz, Prefix pfx, UChar mod_reg_rm )
+const HChar* nameIRegG ( Int sz, Prefix pfx, UChar mod_reg_rm )
{
return nameIReg( sz, gregOfRexRM(pfx,mod_reg_rm),
toBool(sz==1 && !haveREX(pfx)) );
@@ -1332,7 +1332,7 @@
}
static
-HChar* nameIRegE ( Int sz, Prefix pfx, UChar mod_reg_rm )
+const HChar* nameIRegE ( Int sz, Prefix pfx, UChar mod_reg_rm )
{
return nameIReg( sz, eregOfRexRM(pfx,mod_reg_rm),
toBool(sz==1 && !haveREX(pfx)) );
@@ -1891,7 +1891,7 @@
/* Condition codes, using the AMD encoding. */
-static HChar* name_AMD64Condcode ( AMD64Condcode cond )
+static const HChar* name_AMD64Condcode ( AMD64Condcode cond )
{
switch (cond) {
case AMD64CondO: return "o";
@@ -2069,47 +2069,47 @@
/* -------------- Helpers for disassembly printing. -------------- */
-static HChar* nameGrp1 ( Int opc_aux )
+static const HChar* nameGrp1 ( Int opc_aux )
{
- static HChar* grp1_names[8]
+ static const HChar* grp1_names[8]
= { "add", "or", "adc", "sbb", "and", "sub", "xor", "cmp" };
if (opc_aux < 0 || opc_aux > 7) vpanic("nameGrp1(amd64)");
return grp1_names[opc_aux];
}
-static HChar* nameGrp2 ( Int opc_aux )
+static const HChar* nameGrp2 ( Int opc_aux )
{
- static HChar* grp2_names[8]
+ static const HChar* grp2_names[8]
= { "rol", "ror", "rcl", "rcr", "shl", "shr", "shl", "sar" };
if (opc_aux < 0 || opc_aux > 7) vpanic("nameGrp2(amd64)");
return grp2_names[opc_aux];
}
-static HChar* nameGrp4 ( Int opc_aux )
+static const HChar* nameGrp4 ( Int opc_aux )
{
- static HChar* grp4_names[8]
+ static const HChar* grp4_names[8]
= { "inc", "dec", "???", "???", "???", "???", "???", "???" };
if (opc_aux < 0 || opc_aux > 1) vpanic("nameGrp4(amd64)");
return grp4_names[opc_aux];
}
-static HChar* nameGrp5 ( Int opc_aux )
+static const HChar* nameGrp5 ( Int opc_aux )
{
- static HChar* grp5_names[8]
+ static const HChar* grp5_names[8]
= { "inc", "dec", "call*", "call*", "jmp*", "jmp*", "push", "???" };
if (opc_aux < 0 || opc_aux > 6) vpanic("nameGrp5(amd64)");
return grp5_names[opc_aux];
}
-static HChar* nameGrp8 ( Int opc_aux )
+static const HChar* nameGrp8 ( Int opc_aux )
{
- static HChar* grp8_names[8]
+ static const HChar* grp8_names[8]
= { "???", "???", "???", "???", "bt", "bts", "btr", "btc" };
if (opc_aux < 4 || opc_aux > 7) vpanic("nameGrp8(amd64)");
return grp8_names[opc_aux];
}
-//.. static HChar* nameSReg ( UInt sreg )
+//.. static const HChar* nameSReg ( UInt sreg )
//.. {
//.. switch (sreg) {
//.. case R_ES: return "%es";
@@ -2122,17 +2122,17 @@
//.. }
//.. }
-static HChar* nameMMXReg ( Int mmxreg )
+static const HChar* nameMMXReg ( Int mmxreg )
{
- static HChar* mmx_names[8]
+ static const HChar* mmx_names[8]
= { "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7" };
if (mmxreg < 0 || mmxreg > 7) vpanic("nameMMXReg(amd64,guest)");
return mmx_names[mmxreg];
}
-static HChar* nameXMMReg ( Int xmmreg )
+static const HChar* nameXMMReg ( Int xmmreg )
{
- static HChar* xmm_names[16]
+ static const HChar* xmm_names[16]
= { "%xmm0", "%xmm1", "%xmm2", "%xmm3",
"%xmm4", "%xmm5", "%xmm6", "%xmm7",
"%xmm8", "%xmm9", "%xmm10", "%xmm11",
@@ -2141,7 +2141,7 @@
return xmm_names[xmmreg];
}
-static HChar* nameMMXGran ( Int gran )
+static const HChar* nameMMXGran ( Int gran )
{
switch (gran) {
case 0: return "b";
@@ -2152,7 +2152,7 @@
}
}
-static HChar nameISize ( Int size )
+static const HChar nameISize ( Int size )
{
switch (size) {
case 8: return 'q';
@@ -2163,9 +2163,9 @@
}
}
-static HChar* nameYMMReg ( Int ymmreg )
+static const HChar* nameYMMReg ( Int ymmreg )
{
- static HChar* ymm_names[16]
+ static const HChar* ymm_names[16]
= { "%ymm0", "%ymm1", "%ymm2", "%ymm3",
"%ymm4", "%ymm5", "%ymm6", "%ymm7",
"%ymm8", "%ymm9", "%ymm10", "%ymm11",
@@ -2239,7 +2239,7 @@
*/
static
void make_redzone_AbiHint ( VexAbiInfo* vbi,
- IRTemp new_rsp, IRTemp nia, HChar* who )
+ IRTemp new_rsp, IRTemp nia, const HChar* who )
{
Int szB = vbi->guest_stack_redzone_size;
vassert(szB >= 0);
@@ -2266,7 +2266,7 @@
/*------------------------------------------------------------*/
static
-HChar* segRegTxt ( Prefix pfx )
+const HChar* segRegTxt ( Prefix pfx )
{
if (pfx & PFX_CS) return "%cs:";
if (pfx & PFX_DS) return "%ds:";
@@ -2793,7 +2793,7 @@
Bool keep,
Int size,
Long delta0,
- HChar* t_amd64opc )
+ const HChar* t_amd64opc )
{
HChar dis_buf[50];
Int len;
@@ -2909,7 +2909,7 @@
Bool keep,
Int size,
Long delta0,
- HChar* t_amd64opc )
+ const HChar* t_amd64opc )
{
HChar dis_buf[50];
Int len;
@@ -3117,7 +3117,7 @@
IROp op8,
Bool keep,
Long delta,
- HChar* t_amd64opc )
+ const HChar* t_amd64opc )
{
Int size4 = imin(size,4);
IRType ty = szToITy(size);
@@ -3380,7 +3380,7 @@
Prefix pfx,
Long delta, UChar modrm,
Int am_sz, Int d_sz, Int sz, IRExpr* shift_expr,
- HChar* shift_expr_txt, Bool* decode_OK )
+ const HChar* shift_expr_txt, Bool* decode_OK )
{
/* delta on entry points at the modrm byte. */
HChar dis_buf[50];
@@ -3764,7 +3764,7 @@
RDX:RAX/EDX:EAX/DX:AX/AX.
*/
static void codegen_mulL_A_D ( Int sz, Bool syned,
- IRTemp tmp, HChar* tmp_txt )
+ IRTemp tmp, const HChar* tmp_txt )
{
IRType ty = szToITy(sz);
IRTemp t1 = newTemp(ty);
@@ -4247,7 +4247,7 @@
static
void dis_string_op( void (*dis_OP)( Int, IRTemp, Prefix pfx ),
- Int sz, HChar* name, Prefix pfx )
+ Int sz, const HChar* name, Prefix pfx )
{
IRTemp t_inc = newTemp(Ity_I64);
/* Really we ought to inspect the override prefixes, but we don't.
@@ -4397,7 +4397,7 @@
void dis_REP_op ( /*MOD*/DisResult* dres,
AMD64Condcode cond,
void (*dis_OP)(Int, IRTemp, Prefix),
- Int sz, Addr64 rip, Addr64 rip_next, HChar* name,
+ Int sz, Addr64 rip, Addr64 rip_next, const HChar* name,
Prefix pfx )
{
IRTemp t_inc = newTemp(Ity_I64);
@@ -4881,7 +4881,7 @@
Need to check ST(0)'s tag on read, but not on write.
*/
static
-void fp_do_op_mem_ST_0 ( IRTemp addr, HChar* op_txt, HChar* dis_buf,
+void fp_do_op_mem_ST_0 ( IRTemp addr, const HChar* op_txt, HChar* dis_buf,
IROp op, Bool dbl )
{
DIP("f%s%c %s\n", op_txt, dbl?'l':'s', dis_buf);
@@ -4907,7 +4907,7 @@
Need to check ST(0)'s tag on read, but not on write.
*/
static
-void fp_do_oprev_mem_ST_0 ( IRTemp addr, HChar* op_txt, HChar* dis_buf,
+void fp_do_oprev_mem_ST_0 ( IRTemp addr, const HChar* op_txt, HChar* dis_buf,
IROp op, Bool dbl )
{
DIP("f%s%c %s\n", op_txt, dbl?'l':'s', dis_buf);
@@ -4933,7 +4933,7 @@
Check dst and src tags when reading but not on write.
*/
static
-void fp_do_op_ST_ST ( HChar* op_txt, IROp op, UInt st_src, UInt st_dst,
+void fp_do_op_ST_ST ( const HChar* op_txt, IROp op, UInt st_src, UInt st_dst,
Bool pop_after )
{
DIP("f%s%s st(%u), st(%u)\n", op_txt, pop_after?"p":"", st_src, st_dst );
@@ -4952,7 +4952,7 @@
Check dst and src tags when reading but not on write.
*/
static
-void fp_do_oprev_ST_ST ( HChar* op_txt, IROp op, UInt st_src, UInt st_dst,
+void fp_do_oprev_ST_ST ( const HChar* op_txt, IROp op, UInt st_src, UInt st_dst,
Bool pop_after )
{
DIP("f%s%s st(%u), st(%u)\n", op_txt, pop_after?"p":"", st_src, st_dst );
@@ -6694,7 +6694,7 @@
Prefix pfx,
Long delta,
UChar opc,
- HChar* name,
+ const HChar* name,
Bool show_granularity )
{
HChar dis_buf[50];
@@ -6709,7 +6709,7 @@
Bool invG = False;
IROp op = Iop_INVALID;
void* hAddr = NULL;
- HChar* hName = NULL;
+ const HChar* hName = NULL;
Bool eLeft = False;
# define XXX(_name) do { hAddr = &_name; hName = #_name; } while (0)
@@ -6842,7 +6842,7 @@
static ULong dis_MMX_shiftG_byE ( VexAbiInfo* vbi,
Prefix pfx, Long delta,
- HChar* opname, IROp op )
+ const HChar* opname, IROp op )
{
HChar dis_buf[50];
Int alen, size;
@@ -6917,7 +6917,7 @@
straight copy of dis_SSE_shiftE_imm. */
static
-ULong dis_MMX_shiftE_imm ( Long delta, HChar* opname, IROp op )
+ULong dis_MMX_shiftE_imm ( Long delta, const HChar* opname, IROp op )
{
Bool shl, shr, sar;
UChar rm = getUChar(delta);
@@ -7416,7 +7416,7 @@
Int sz,
IRExpr* shift_amt,
Bool amt_is_literal,
- HChar* shift_amt_txt,
+ const HChar* shift_amt_txt,
Bool left_shift )
{
/* shift_amt :: Ity_I8 is the amount to shift. shift_amt_txt is used
@@ -7582,7 +7582,7 @@
typedef enum { BtOpNone, BtOpSet, BtOpReset, BtOpComp } BtOp;
-static HChar* nameBtOp ( BtOp op )
+static const HChar* nameBtOp ( BtOp op )
{
switch (op) {
case BtOpNone: return "";
@@ -8301,7 +8301,7 @@
static ULong dis_SSE_E_to_G_all_wrk (
VexAbiInfo* vbi,
Prefix pfx, Long delta,
- HChar* opname, IROp op,
+ const HChar* opname, IROp op,
Bool invertG
)
{
@@ -8338,7 +8338,7 @@
static
ULong dis_SSE_E_to_G_all ( VexAbiInfo* vbi,
Prefix pfx, Long delta,
- HChar* opname, IROp op )
+ const HChar* opname, IROp op )
{
return dis_SSE_E_to_G_all_wrk( vbi, pfx, delta, opname, op, False );
}
@@ -8348,7 +8348,7 @@
static
ULong dis_SSE_E_to_G_all_invG ( VexAbiInfo* vbi,
Prefix pfx, Long delta,
- HChar* opname, IROp op )
+ const HChar* opname, IROp op )
{
return dis_SSE_E_to_G_all_wrk( vbi, pfx, delta, opname, op, True );
}
@@ -8358,7 +8358,7 @@
static ULong dis_SSE_E_to_G_lo32 ( VexAbiInfo* vbi,
Prefix pfx, Long delta,
- HChar* opname, IROp op )
+ const HChar* opname, IROp op )
{
HChar dis_buf[50];
Int alen;
@@ -8394,7 +8394,7 @@
static ULong dis_SSE_E_to_G_lo64 ( VexAbiInfo* vbi,
Prefix pfx, Long delta,
- HChar* opname, IROp op )
+ const HChar* opname, IROp op )
{
HChar dis_buf[50];
Int alen;
@@ -8431,7 +8431,7 @@
static ULong dis_SSE_E_to_G_unary_all (
VexAbiInfo* vbi,
Prefix pfx, Long delta,
- HChar* opname, IROp op
+ const HChar* opname, IROp op
)
{
HChar dis_buf[50];
@@ -8462,7 +8462,7 @@
static ULong dis_SSE_E_to_G_unary_lo32 (
VexAbiInfo* vbi,
Prefix pfx, Long delta,
- HChar* opname, IROp op
+ const HChar* opname, IROp op
)
{
/* First we need to get the old G value and patch the low 32 bits
@@ -8506,7 +8506,7 @@
static ULong dis_SSE_E_to_G_unary_lo64 (
VexAbiInfo* vbi,
Prefix pfx, Long delta,
- HChar* opname, IROp op
+ const HChar* opname, IROp op
)
{
/* First we need to get the old G value and patch the low 64 bits
@@ -8552,7 +8552,7 @@
static ULong dis_SSEint_E_to_G(
VexAbiInfo* vbi,
Prefix pfx, Long delta,
- HChar* opname, IROp op,
+ const HChar* opname, IROp op,
Bool eLeft
)
{
@@ -8707,7 +8707,7 @@
static Long dis_SSE_cmp_E_to_G ( VexAbiInfo* vbi,
Prefix pfx, Long delta,
- HChar* opname, Bool all_lanes, Int sz )
+ const HChar* opname, Bool all_lanes, Int sz )
{
Long delta0 = delta;
HChar dis_buf[50];
@@ -8783,7 +8783,7 @@
static ULong dis_SSE_shiftG_byE ( VexAbiInfo* vbi,
Prefix pfx, Long delta,
- HChar* opname, IROp op )
+ const HChar* opname, IROp op )
{
HChar dis_buf[50];
Int alen, size;
@@ -8859,7 +8859,7 @@
static
ULong dis_SSE_shiftE_imm ( Prefix pfx,
- Long delta, HChar* opname, IROp op )
+ Long delta, const HChar* opname, IROp op )
{
Bool shl, shr, sar;
UChar rm = getUChar(delta);
@@ -9606,7 +9606,7 @@
HChar dis_buf[50];
IRTemp sV = newTemp(Ity_V128);
UChar modrm = getUChar(delta);
- HChar* strV = writesYmm ? "v" : "";
+ const HChar* strV = writesYmm ? "v" : "";
IRTemp addr = IRTemp_INVALID;
if (epartIsReg(modrm)) {
assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
@@ -10778,7 +10778,7 @@
UChar modrm = getUChar(delta);
IRTemp arg64 = newTemp(Ity_I64);
UInt rG = gregOfRexRM(pfx,modrm);
- HChar* mbV = isAvx ? "v" : "";
+ const HChar* mbV = isAvx ? "v" : "";
if (epartIsReg(modrm)) {
UInt rE = eregOfRexRM(pfx,modrm);
assign( arg64, getXMMRegLane64(rE, 0) );
@@ -11531,7 +11531,7 @@
&& !epartIsReg(getUChar(delta))
&& gregLO3ofRM(getUChar(delta)) >= 0
&& gregLO3ofRM(getUChar(delta)) <= 3) {
- HChar* hintstr = "??";
+ const HChar* hintstr = "??";
modrm = getUChar(delta);
vassert(!epartIsReg(modrm));
@@ -14243,7 +14243,7 @@
IRTemp eV = newTemp(Ity_V128);
IRTemp gV = newTemp(Ity_V128);
Bool isAdd = opc == 0x7C;
- HChar* str = isAdd ? "add" : "sub";
+ const HChar* str = isAdd ? "add" : "sub";
modrm = getUChar(delta);
UInt rG = gregOfRexRM(pfx,modrm);
if (epartIsReg(modrm)) {
@@ -14268,7 +14268,7 @@
IRTemp eV = newTemp(Ity_V128);
IRTemp gV = newTemp(Ity_V128);
Bool isAdd = opc == 0x7C;
- HChar* str = isAdd ? "add" : "sub";
+ const HChar* str = isAdd ? "add" : "sub";
modrm = getUChar(delta);
UInt rG = gregOfRexRM(pfx,modrm);
if (epartIsReg(modrm)) {
@@ -14474,7 +14474,7 @@
IRTemp addr = IRTemp_INVALID;
Int alen = 0;
HChar dis_buf[50];
- HChar* str = "???";
+ const HChar* str = "???";
IROp opV64 = Iop_INVALID;
IROp opCatO = Iop_CatOddLanes16x4;
IROp opCatE = Iop_CatEvenLanes16x4;
@@ -14689,7 +14689,7 @@
/* 0F 38 07 = PHSUBSW -- 16x4 signed qsub across from E (mem or
mmx) and G to G (mmx). */
if (haveNo66noF2noF3(pfx) && sz == 4) {
- HChar* str = "???";
+ const HChar* str = "???";
IROp opV64 = Iop_INVALID;
...
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