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From: Josef W. <Jos...@gm...> - 2012-09-24 18:43:56
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Am 24.09.2012 20:18, schrieb Carl E. Love: > I was just looking into the POWER architectures a bit more to make sure > they would be reasonably easy to support. Just to be clear, are there > any Valgrind restrictions on the cache sizes, specifically must be a > power of 2? The simulator in Cachegrind/Callgrind currently has various constrains about the sizes: * the cache line size in bytes must be a power of two (at least 16B) * the number of sets (= cache size / line size / associativity) must be a power of two. This is used to allow fast set calculation from address of a memory access. It is already now the case that sometimes values are adjusted (with an corresponding warning printed) to make the simulator happy. If that seems impossible, the simulator will error out, and ask the user to specify parameters via command line. However, this all is the responsibility of the tool. The interface asking for hardware parameters seems fine to me, and should be able to return any numbers. > I see the Power 5 has an L2 unified cache of 1.875MB and and L3 unified, > shared cache of size 36MB. I was doing some cache studies last year and > I remember there being issues where the cache size must be a power of 2. > I don't remember what tool it was now that had that restriction. > > Similarly, must the Valgrind cache associativity be a power of 2? No. > The > POWER 5 processor's L2 cache is 10-way set associative. Josef |