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From: Carl E. L. <ce...@li...> - 2012-09-24 18:20:12
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On Fri, 2012-09-21 at 13:01 -0400, Florian Krohm wrote:
> We had a discussion about this a few weeks back. Here are my thoughts.
>
>
> Objective:
> ----------
> Have coregrind query the properties of the host's cache system. Make
> this information available in a simple interface that hides all
> architecture-specific details e.g. the existence of a cpuid instruction.
>
>
> Benefits:
> ---------
> This is conceptually cleaner than the status quo. Detection of cache
> properties does not belong in the realm of the tools. Additionally,
> if several tools required information about caches there would be code
> duplication.
>
>
> Representation of cache information:
> ------------------------------------
>
> /* The various kinds of caches */
> typedef enum {
> DATA_CACHE,
> INSN_CACHE,
> DATA_INSN_CACHE // combined data and insn cache
> } cache_kind;
>
> /* Information about a particular cache */
> typedef struct {
> cache_kind kind;
> UInt level; /* level this cache is at, e.g. 1 for L1 cache */
> UInt sizeB; /* size of this cache in bytes */
> UInt line_sizeB; /* cache line size in bytes */
> UInt associativity;
> } cache_t;
>
> /* Information about the cache system as a whole */
> typedef struct {
> UInt num_levels;
> UInt num_caches;
> /* Unordered array of caches for this host. NULL if there are
> no caches. Users can assume that the array contains at most one
> cache of a given kind per cache level. */
> cache_t *caches;
> } cacheinfo_t;
>
I was just looking into the POWER architectures a bit more to make sure
they would be reasonably easy to support. Just to be clear, are there
any Valgrind restrictions on the cache sizes, specifically must be a
power of 2?
I see the Power 5 has an L2 unified cache of 1.875MB and and L3 unified,
shared cache of size 36MB. I was doing some cache studies last year and
I remember there being issues where the cache size must be a power of 2.
I don't remember what tool it was now that had that restriction.
Similarly, must the Valgrind cache associativity be a power of 2? The
POWER 5 processor's L2 cache is 10-way set associative.
<snip>
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