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From: Petar J. <mip...@gm...> - 2012-09-17 12:18:56
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Hi everyone,
Loongson platform has some specifics which diverge from MIPS32 spec.
This mostly relates to usage of odd registers in FPU instructions, and thus
we should (mostly) avoid use of odd single precision FP registers for Loongson.
Thus, a fix (see down below) for this can be made in getAllocableRegs_MIPS.
It would be, however, nice to have that change conditional to Loongson platform,
but VexArchInfo is not available at that point.
So, does anybody think there is a clean way to get VexArchInfo at
getAllocableRegs_PLATFORM, or we should just apply the change to fit
Loongson in this case (we measured it, and no performance impact has been
seen on any of the benchmarks we ran)? Or this could be resolved differently?
Thanks for the feedback.
Petar
Index: VEX/priv/host_mips_defs.c
===================================================================
--- VEX/priv/host_mips_defs.c (revision 2491)
+++ VEX/priv/host_mips_defs.c (working copy)
@@ -552,9 +552,9 @@
void getAllocableRegs_MIPS(Int * nregs, HReg ** arr, Bool mode64)
{
if (mode64)
- *nregs = 27;
+ *nregs = 24;
else
- *nregs = 34;
+ *nregs = 29;
UInt i = 0;
*arr = LibVEX_Alloc(*nregs * sizeof(HReg));
@@ -595,16 +595,13 @@
// FP = frame pointer
// RA = link register
// + PC, HI and LO
+ (*arr)[i++] = hregMIPS_F16(mode64);
+ (*arr)[i++] = hregMIPS_F18(mode64);
(*arr)[i++] = hregMIPS_F20(mode64);
- (*arr)[i++] = hregMIPS_F21(mode64);
(*arr)[i++] = hregMIPS_F22(mode64);
- (*arr)[i++] = hregMIPS_F23(mode64);
(*arr)[i++] = hregMIPS_F24(mode64);
- (*arr)[i++] = hregMIPS_F25(mode64);
(*arr)[i++] = hregMIPS_F26(mode64);
- (*arr)[i++] = hregMIPS_F27(mode64);
(*arr)[i++] = hregMIPS_F28(mode64);
- (*arr)[i++] = hregMIPS_F29(mode64);
(*arr)[i++] = hregMIPS_F30(mode64);
if (!mode64) {
/* Fake double floating point */
@@ -616,8 +613,6 @@
(*arr)[i++] = hregMIPS_D5();
(*arr)[i++] = hregMIPS_D6();
(*arr)[i++] = hregMIPS_D7();
- (*arr)[i++] = hregMIPS_D8();
- (*arr)[i++] = hregMIPS_D9();
}
vassert(i == *nregs);
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