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From: <sv...@va...> - 2012-09-09 01:11:10
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petarj 2012-09-09 02:10:59 +0100 (Sun, 09 Sep 2012)
New Revision: 2519
Log:
Correcting how load/store doubles are modelled on MIPS for big-endian.
One of the previous changes, r2511, was correct for little-endian and introduced
a regression for big-endian MIPS. This corrects the endianness issues.
Modified files:
trunk/priv/guest_mips_toIR.c
trunk/priv/host_mips_isel.c
Modified: trunk/priv/host_mips_isel.c (+1 -1)
===================================================================
--- trunk/priv/host_mips_isel.c 2012-09-07 22:18:42 +01:00 (rev 2518)
+++ trunk/priv/host_mips_isel.c 2012-09-09 02:10:59 +01:00 (rev 2519)
@@ -2463,7 +2463,7 @@
}
/* --------- LOAD --------- */
- if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) {
+ if (e->tag == Iex_Load) {
HReg r_dst = newVRegD(env);
MIPSAMode *am_addr;
vassert(e->Iex.Load.ty == Ity_F64);
Modified: trunk/priv/guest_mips_toIR.c (+16 -0)
===================================================================
--- trunk/priv/guest_mips_toIR.c 2012-09-07 22:18:42 +01:00 (rev 2518)
+++ trunk/priv/guest_mips_toIR.c 2012-09-09 02:10:59 +01:00 (rev 2519)
@@ -889,8 +889,13 @@
IRTemp t4 = newTemp(Ity_I32);
IRTemp t5 = newTemp(Ity_I64);
+#if defined (_MIPSEL)
assign(t0, getFReg(dregNo));
assign(t1, getFReg(dregNo + 1));
+#elif defined (_MIPSEB)
+ assign(t0, getFReg(dregNo + 1));
+ assign(t1, getFReg(dregNo));
+#endif
assign(t3, unop(Iop_ReinterpF32asI32, mkexpr(t0)));
assign(t4, unop(Iop_ReinterpF32asI32, mkexpr(t1)));
@@ -920,8 +925,13 @@
assign(t6, unop(Iop_ReinterpF64asI64, mkexpr(t1)));
assign(t4, unop(Iop_64HIto32, mkexpr(t6))); // hi
assign(t5, unop(Iop_64to32, mkexpr(t6))); //lo
+#if defined (_MIPSEL)
putFReg(dregNo, unop(Iop_ReinterpI32asF32, mkexpr(t5)));
putFReg(dregNo + 1, unop(Iop_ReinterpI32asF32, mkexpr(t4)));
+#elif defined (_MIPSEB)
+ putFReg(dregNo + 1, unop(Iop_ReinterpI32asF32, mkexpr(t5)));
+ putFReg(dregNo, unop(Iop_ReinterpI32asF32, mkexpr(t4)));
+#endif
}
static void setFPUCondCode(IRExpr * e, UInt cc)
@@ -1567,9 +1577,15 @@
{ //D
DIP("recip.d f%d, f%d\n", fd, fs);
IRExpr *rm = get_IR_roundingmode();
+#if defined (_MIPSEL)
putDReg(fd, triop(Iop_DivF64, rm,
unop(Iop_ReinterpI64asF64,
mkU64(0x3FF0000000000000ULL)), getDReg(fs)));
+#elif defined (_MIPSEB)
+ putDReg(fd, triop(Iop_DivF64, rm,
+ unop(Iop_ReinterpI64asF64,
+ mkU64(0x000000003FF00000ULL)), getDReg(fs)));
+#endif
break;
}
default:
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