Re: [Valgrind-users] helgrind and atomic operations

[Patrick J. L. <lop...@gm...>]

On Sun, Aug 26, 2012 at 2:06 AM, David Faure <fa...@kd...> wrote:
>
> Marc Mutz said "
> The standard says it's racy, but the implementation of
> std::atomic::load(memory_order_acquire) won't look different. Simple reads
> and writes on x86 are already sequentially consistent.

I do not think this is true.  Loads on x86 do have acquire semantics,
and stores do have release semantics, but that is not the same as
sequential consistency.  If loads and stores on x86 were "already
sequentially consistent", there would be no need for the mfence
instruction...

And as Julian points out, the compiler has plenty of license to
reorder things even if the CPU does not.  Dealing with all of this is
why C++11 has a memory model.

Out of curiosity, is Helgrind expected to generate errors for
correctly-implemented lock-free algorithms?  (That is, algorithms with
correct memory barriers and no mutexes?)

 - Pat