Re: [Valgrind-developers] mtV : memcheck VA bits

[Josef W. <Jos...@gm...>]

Am 19.06.2012 18:50, schrieb Julian Seward:
> On Sunday, June 17, 2012, Philippe Waroquiers wrote:
>
>>> Use LoadLocked and StoreConditional instructions, as on MIPS.
>>> These sense the state of the cache line, and implement a "greedy"
>>> solution.  Your code provides the fixup when greedy fails
>>> (usually: try again, after re-fetch and re-modify.)
>>
>> Are the LL/SC instructions not suffering from the same performance
>> degradation as the x86/amd64 atomic instructions ?
>> (cfr the unacceptable performance degration in memcheck when
>> adding one atomic instruction in the STORE helperc).
>>
>> I have very bad knowledge of all these atomic things and similar,
>> but I am guessing that there is no order of magnitude difference
>> of performance between these approaches.
>
> I would agree with your guess.  In both cases (LL/SC or LOCK), some
> kind of global communication across all cores is implied, in the
> worst case.

Isn't the important thing the common case? If the address of a lock
or a memory cell to observe (LL/SC) is already owned
(=exclusive/modified state) by a private L1 of a core, another
modification by that core should not trigger any transaction
to the outside, if the L1 is write-back.
Hmm. In the end, it probably does not change much.

More interesting would be to use HW transactional memory for this
(only available with Haswell processors next year. Or BG/Q).

Josef

>
> One thing I do know (from testing on an old Core 2), is that the cost
> of LOCK depends on how far down the cache hierarchy the line in question
> is.  In the case where the line is in that core's D1, then the cost was
> "only" about 10-15 cycles instead of the often-rumoured 100+ cycles.
>
> But I am not claiming to understand anything much about this, really;
> in particular I have no idea if such performance variations are something
> that it would be safe for us to depend on in the general case.
>
> J
>
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