Menu
▾
▴
[Valgrind-developers] vex: r2383: Fill in some missing AVX insns:
|
From: <sv...@va...> - 2012-06-14 23:32:11
|
sewardj 2012-06-15 00:32:02 +0100 (Fri, 15 Jun 2012)
New Revision: 2383
Log:
Fill in some missing AVX insns:
VANDPS = VEX.NDS.256.0F.WIG 54 /r
VANDNPD = VEX.NDS.256.66.0F.WIG 55 /r
ANDNPS = VEX.NDS.256.0F.WIG 55 /r
VORPD = VEX.NDS.256.66.0F.WIG 56 /r
VORPS = VEX.NDS.256.0F.WIG 56 /r
VXORPS = VEX.NDS.256.0F.WIG 57 /r
VDIVPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.0F.WIG 5E /r
Modified version of a patch by Jakub Jelinek, ja...@re...
(bug 273475 comment 96)
Modified files:
trunk/priv/guest_amd64_toIR.c
trunk/priv/host_amd64_isel.c
trunk/priv/ir_defs.c
trunk/pub/libvex_ir.h
Modified: trunk/pub/libvex_ir.h (+2 -0)
===================================================================
--- trunk/pub/libvex_ir.h 2012-06-14 09:51:35 +01:00 (rev 2382)
+++ trunk/pub/libvex_ir.h 2012-06-15 00:32:02 -23:00 (rev 2383)
@@ -1436,7 +1436,9 @@
Iop_V128HLtoV256, // (V128,V128)->V256, first arg is most signif
Iop_AndV256,
+ Iop_OrV256,
Iop_XorV256,
+ Iop_NotV256,
/* ------------------ 256-bit SIMD FP. ------------------ */
Iop_Add64Fx4,
Modified: trunk/priv/ir_defs.c (+10 -9)
===================================================================
--- trunk/priv/ir_defs.c 2012-06-14 09:51:35 +01:00 (rev 2382)
+++ trunk/priv/ir_defs.c 2012-06-15 00:32:02 -23:00 (rev 2383)
@@ -996,7 +996,9 @@
case Iop_Mul32Fx8: vex_printf("Mul32Fx8"); return;
case Iop_Div32Fx8: vex_printf("Div32Fx8"); return;
case Iop_AndV256: vex_printf("AndV256"); return;
+ case Iop_OrV256: vex_printf("OrV256"); return;
case Iop_XorV256: vex_printf("XorV256"); return;
+ case Iop_NotV256: vex_printf("NotV256"); return;
default: vpanic("ppIROp(1)");
}
@@ -2796,15 +2798,11 @@
case Iop_64x4toV256:
QUATERNARY(Ity_I64, Ity_I64, Ity_I64, Ity_I64, Ity_V256);
- case Iop_Add64Fx4:
- case Iop_Sub64Fx4:
- case Iop_Mul64Fx4:
- case Iop_Div64Fx4:
- case Iop_Add32Fx8:
- case Iop_Sub32Fx8:
- case Iop_Mul32Fx8:
- case Iop_Div32Fx8:
- case Iop_AndV256:
+ case Iop_Add64Fx4: case Iop_Sub64Fx4:
+ case Iop_Mul64Fx4: case Iop_Div64Fx4:
+ case Iop_Add32Fx8: case Iop_Sub32Fx8:
+ case Iop_Mul32Fx8: case Iop_Div32Fx8:
+ case Iop_AndV256: case Iop_OrV256:
case Iop_XorV256:
BINARY(Ity_V256,Ity_V256, Ity_V256);
@@ -2814,6 +2812,9 @@
case Iop_V128HLtoV256:
BINARY(Ity_V128,Ity_V128, Ity_V256);
+ case Iop_NotV256:
+ UNARY(Ity_V256, Ity_V256);
+
default:
ppIROp(op);
vpanic("typeOfPrimop");
Modified: trunk/priv/guest_amd64_toIR.c (+49 -4)
===================================================================
--- trunk/priv/guest_amd64_toIR.c 2012-06-14 09:51:35 +01:00 (rev 2382)
+++ trunk/priv/guest_amd64_toIR.c 2012-06-15 00:32:02 -23:00 (rev 2383)
@@ -19887,10 +19887,8 @@
Int alen = 0;
vassert(1==getVexL(pfx)/*256*/ && 0==getRexW(pfx)/*WIG?*/);
- // Hmm. we don't actually have Iop_NotV256 (yet). Hence kludge:
- vassert(!invertLeftArg);
- assign(tSL, /* invertLeftArg ? unop(Iop_NotV256, getYMMReg(rSL))
- : */ getYMMReg(rSL));
+ assign(tSL, invertLeftArg ? unop(Iop_NotV256, getYMMReg(rSL))
+ : getYMMReg(rSL));
if (epartIsReg(modrm)) {
UInt rSR = eregOfRexRM(pfx, modrm);
@@ -20740,6 +20738,12 @@
uses_vvvv, vbi, pfx, delta, "vandps", Iop_AndV128 );
goto decode_success;
}
+ /* VANDPS = VEX.NDS.256.0F.WIG 54 /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vandps", Iop_AndV256 );
+ goto decode_success;
+ }
break;
case 0x55:
@@ -20751,6 +20755,13 @@
NULL, True/*invertLeftArg*/, False/*swapArgs*/ );
goto decode_success;
}
+ /* VANDNPD = VEX.NDS.256.66.0F.WIG 55 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vandpd", Iop_AndV256,
+ NULL, True/*invertLeftArg*/, False/*swapArgs*/ );
+ goto decode_success;
+ }
/* VANDNPS = VEX.NDS.128.0F.WIG 55 /r */
if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
delta = dis_VEX_NDS_128_AnySimdPfx_0F_WIG(
@@ -20758,6 +20769,13 @@
NULL, True/*invertLeftArg*/, False/*swapArgs*/ );
goto decode_success;
}
+ /* VANDNPS = VEX.NDS.256.0F.WIG 55 /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_VEX_NDS_256_AnySimdPfx_0F_WIG(
+ uses_vvvv, vbi, pfx, delta, "vandps", Iop_AndV256,
+ NULL, True/*invertLeftArg*/, False/*swapArgs*/ );
+ goto decode_success;
+ }
break;
case 0x56:
@@ -20768,6 +20786,13 @@
uses_vvvv, vbi, pfx, delta, "vorpd", Iop_OrV128 );
goto decode_success;
}
+ /* VORPD r/m, rV, r ::: r = rV | r/m */
+ /* VORPD = VEX.NDS.256.66.0F.WIG 56 /r */
+ if (have66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vorpd", Iop_OrV256 );
+ goto decode_success;
+ }
/* VORPS r/m, rV, r ::: r = rV | r/m */
/* VORPS = VEX.NDS.128.0F.WIG 56 /r */
if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
@@ -20775,6 +20800,13 @@
uses_vvvv, vbi, pfx, delta, "vorps", Iop_OrV128 );
goto decode_success;
}
+ /* VORPS r/m, rV, r ::: r = rV | r/m */
+ /* VORPS = VEX.NDS.256.0F.WIG 56 /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vorps", Iop_OrV256 );
+ goto decode_success;
+ }
break;
case 0x57:
@@ -20799,6 +20831,13 @@
uses_vvvv, vbi, pfx, delta, "vxorps", Iop_XorV128 );
goto decode_success;
}
+ /* VXORPS r/m, rV, r ::: r = rV ^ r/m */
+ /* VXORPS = VEX.NDS.256.0F.WIG 57 /r */
+ if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
+ delta = dis_AVX256_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vxorps", Iop_XorV256 );
+ goto decode_success;
+ }
break;
case 0x58:
@@ -21035,6 +21074,12 @@
uses_vvvv, vbi, pfx, delta, "vdivss", Iop_Div32F0x4 );
goto decode_success;
}
+ /* VDIVPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.0F.WIG 5E /r */
+ if (haveNo66noF2noF3(pfx) && 0==getVexL(pfx)/*128*/) {
+ delta = dis_AVX128_E_V_to_G(
+ uses_vvvv, vbi, pfx, delta, "vdivps", Iop_Div32Fx4 );
+ goto decode_success;
+ }
/* VDIVPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.0F.WIG 5E /r */
if (haveNo66noF2noF3(pfx) && 1==getVexL(pfx)/*256*/) {
delta = dis_AVX256_E_V_to_G(
Modified: trunk/priv/host_amd64_isel.c (+17 -0)
===================================================================
--- trunk/priv/host_amd64_isel.c 2012-06-14 09:51:35 +01:00 (rev 2382)
+++ trunk/priv/host_amd64_isel.c 2012-06-15 00:32:02 -23:00 (rev 2383)
@@ -3431,6 +3431,22 @@
return;
}
+ if (e->tag == Iex_Unop) {
+ switch (e->Iex.Unop.op) {
+
+ case Iop_NotV256: {
+ HReg argHi, argLo;
+ iselDVecExpr(&argHi, &argLo, env, e->Iex.Unop.arg);
+ *rHi = do_sse_NotV128(env, argHi);
+ *rLo = do_sse_NotV128(env, argLo);
+ return;
+ }
+
+ default:
+ break;
+ } /* switch (e->Iex.Unop.op) */
+ } /* if (e->tag == Iex_Unop) */
+
if (e->tag == Iex_Binop) {
switch (e->Iex.Binop.op) {
@@ -3475,6 +3491,7 @@
}
case Iop_AndV256: op = Asse_AND; goto do_SseReRg;
+ case Iop_OrV256: op = Asse_OR; goto do_SseReRg;
case Iop_XorV256: op = Asse_XOR; goto do_SseReRg;
do_SseReRg:
{
|
