[Valgrind-developers] vex: r2335: Enable FCOMS/FCOMPS on amd64. Fixes #300414.

[<sv...@va...>]

sewardj	2012-05-21 22:51:36 +0100 (Mon, 21 May 2012)

  New Revision: 2335

  Log:
    Enable FCOMS/FCOMPS on amd64.  Fixes #300414.
    (Eliot Moss, mo...@cs...)

  Modified files:
    trunk/priv/guest_amd64_toIR.c


  Modified: trunk/priv/guest_amd64_toIR.c (+36 -30)
===================================================================
--- trunk/priv/guest_amd64_toIR.c	2012-05-21 17:16:13 +01:00 (rev 2334)
+++ trunk/priv/guest_amd64_toIR.c	2012-05-21 22:51:36 +01:00 (rev 2335)
@@ -4999,37 +4999,43 @@
                fp_do_op_mem_ST_0 ( addr, "mul", dis_buf, Iop_MulF64, False );
                break;
 
-//..             case 2: /* FCOM single-real */
-//..                DIP("fcoms %s\n", dis_buf);
-//..                /* This forces C1 to zero, which isn't right. */
-//..                put_C3210( 
-//..                    binop( Iop_And32,
-//..                           binop(Iop_Shl32, 
-//..                                 binop(Iop_CmpF64, 
-//..                                       get_ST(0),
-//..                                       unop(Iop_F32toF64, 
-//..                                            loadLE(Ity_F32,mkexpr(addr)))),
-//..                                 mkU8(8)),
-//..                           mkU32(0x4500)
-//..                    ));
-//..                break;  
-//.. 
-//..             case 3: /* FCOMP single-real */
-//..                DIP("fcomps %s\n", dis_buf);
-//..                /* This forces C1 to zero, which isn't right. */
-//..                put_C3210( 
-//..                    binop( Iop_And32,
-//..                           binop(Iop_Shl32, 
-//..                                 binop(Iop_CmpF64, 
-//..                                       get_ST(0),
-//..                                       unop(Iop_F32toF64, 
-//..                                            loadLE(Ity_F32,mkexpr(addr)))),
-//..                                 mkU8(8)),
-//..                           mkU32(0x4500)
-//..                    ));
-//..                fp_pop();
-//..                break;  
+            case 2: /* FCOM single-real */
+               DIP("fcoms %s\n", dis_buf);
+               /* This forces C1 to zero, which isn't right. */
+               /* The AMD documentation suggests that forcing C1 to
+                  zero is correct (Eliot Moss) */
+               put_C3210( 
+                   unop( Iop_32Uto64,
+                       binop( Iop_And32,
+                              binop(Iop_Shl32, 
+                                    binop(Iop_CmpF64, 
+                                          get_ST(0),
+                                          unop(Iop_F32toF64, 
+                                               loadLE(Ity_F32,mkexpr(addr)))),
+                                    mkU8(8)),
+                              mkU32(0x4500)
+                   )));
+               break;  
 
+            case 3: /* FCOMP single-real */
+               /* The AMD documentation suggests that forcing C1 to
+                  zero is correct (Eliot Moss) */
+               DIP("fcomps %s\n", dis_buf);
+               /* This forces C1 to zero, which isn't right. */
+               put_C3210( 
+                   unop( Iop_32Uto64,
+                       binop( Iop_And32,
+                              binop(Iop_Shl32, 
+                                    binop(Iop_CmpF64, 
+                                          get_ST(0),
+                                          unop(Iop_F32toF64, 
+                                               loadLE(Ity_F32,mkexpr(addr)))),
+                                    mkU8(8)),
+                              mkU32(0x4500)
+                   )));
+               fp_pop();
+               break;  
+
             case 4: /* FSUB single-real */
                fp_do_op_mem_ST_0 ( addr, "sub", dis_buf, Iop_SubF64, False );
                break;