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From: <sv...@va...> - 2012-02-17 15:11:43
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Author: sewardj
Date: 2012-02-17 15:07:09 +0000 (Fri, 17 Feb 2012)
New Revision: 2257
Log:
Accept DMB (mcr 15, 0, rT, c7, c10, 5) for any rT <= 14,
not just when rT = r0.
Modified:
trunk/priv/guest_arm_toIR.c
Modified: trunk/priv/guest_arm_toIR.c
===================================================================
--- trunk/priv/guest_arm_toIR.c 2012-02-16 22:02:14 UTC (rev 2256)
+++ trunk/priv/guest_arm_toIR.c 2012-02-17 15:07:09 UTC (rev 2257)
@@ -14051,6 +14051,19 @@
means we don't know which they are, so the back end has to
re-emit them all when it comes acrosss an IR Fence.
*/
+ /* v6 */ /* mcr 15, 0, rT, c7, c10, 5 */
+ if (0xEE070FBA == (insn & 0xFFFF0FFF)) {
+ UInt rT = INSN(15,12);
+ if (rT <= 14) {
+ /* mcr 15, 0, rT, c7, c10, 5 (v6) equiv to DMB (v7). Data
+ Memory Barrier -- ensures ordering of memory accesses. */
+ stmt( IRStmt_MBE(Imbe_Fence) );
+ DIP("mcr 15, 0, r%u, c7, c10, 5 (data memory barrier)\n", rT);
+ goto decode_success;
+ }
+ /* fall through */
+ }
+ /* other flavours of barrier */
switch (insn) {
case 0xEE070F9A: /* v6 */
/* mcr 15, 0, r0, c7, c10, 4 (v6) equiv to DSB (v7). Data
@@ -14058,12 +14071,6 @@
stmt( IRStmt_MBE(Imbe_Fence) );
DIP("mcr 15, 0, r0, c7, c10, 4 (data synch barrier)\n");
goto decode_success;
- case 0xEE070FBA: /* v6 */
- /* mcr 15, 0, r0, c7, c10, 5 (v6) equiv to DMB (v7). Data
- Memory Barrier -- ensures ordering of memory accesses. */
- stmt( IRStmt_MBE(Imbe_Fence) );
- DIP("mcr 15, 0, r0, c7, c10, 5 (data memory barrier)\n");
- goto decode_success;
case 0xEE070F95: /* v6 */
/* mcr 15, 0, r0, c7, c5, 4 (v6) equiv to ISB (v7).
Instruction Synchronisation Barrier (or Flush Prefetch
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