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From: Carl E. L. <ce...@li...> - 2011-12-22 16:17:20
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This is a re-post as the original posting was rejected by the mailing list.
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Valgrind community:
Please review and comment on the following is a proposal to add Iops to
Valgrind to support Decimal Floating Point (DFP) instructions. The
following proposal includes adding 31 new DFP Iops to support operations
on 32-bit, 64-bit and 128-bit DFP numbers. The intent was to come up with
a minimal and sufficient set for the POWER and s390 architectures to start
with. The hope is that the set of proposed Iops will also be sufficient
for other architectures but I can't say for sure since I do not have access
to the DFP instruction set for any other architectures.
There are seven additional Iops that may need to be added in the future when
DFP support is added for the s390 architecture. For these s390 instructions,
there is no Power equivalent. The names of these Iops is left as
"To Be Determined" (TBD) at the time the support is added. They are called
out here for completeness of all the Iops that may need to be added for s390
DFP support.
The list of proposed DFP Iops will be used to implement the 49 POWER7 DFP
instructions and the 78 s390 DFP instructions. Note that some of the POWER7
and s390 instructions can be emulated using existing Iops and the proposed
new Iops. The instructions that can be emulated have not been explicitly
listed in this proposal.
The IBM Power and s390 systems support 32-bit, 64-bit and 128-bit decimal
floating point (DFP) numbers. The DFP instructions use the existing floating
point registers. The DFP 128-bit operands are stored in registers i and i+1
where i must be even. For example the DFP 128-bit add is done as follows:
lfd 12,48(31) // load the upper 64 bits of the first 128 value in reg 12
lfd 13,56(31) // load the lower 64 bits of the first 128 value in reg 13
addi 0,31,64
mr 9,0
lfd 0,0(9) // load the upper 64 bits of the 128 second value in reg 0
lfd 1,8(9) // load the lower 64 bits of the 128 second value in reg 1
daddq 0,12,0 // do the add of the 128 DFP numbers, result is stored in
// registers 0 and 1. Note, registers 1 and 13 are not
// explicitly listed but are implied
Please note, I will only be adding the IBM POWER series DFP support at this
time. The s390 team will be responsible for doing the Valgrind support for
the s390 at some point in the future.
The following is a list definitions for the notations used in the description
of the proposed new Iops.
Notation Description
---------------------------------------------------------------------------
DFP: Decimal Floating Point number possibly 32-bit, 64-bit, or
128-bit format
D32: 32-bit decimal floating point format These values use F64
registers. The D32 term is used to distinguish the value
from the standard 32-bit floating point value.
D64: 64-bit decimal floating point format. These values use F64
registers. The D64 term is used to distinguish the value
from the standard 64-bit floating point value.
D128: 128-bit decimal floating point format. These values use a pair
of two 64 bit floating point registers (F64). The instruction
only references the first register of the register pair. The
second register is implied.
IRRoundingMode(I32): Indicates the I32 argument is used to hold the
bits that specify the rounding mode to be used
by the instruction.
IRRoundingExceptionModes(I32): Indicates the I32 argument is used to hold the
bits that specify the rounding mode and the bits
that specify the exception mode to be used by
the instruction. The s390 instructions specify
both modes whereas POWER does not specify either
mode.
IRRoundingModeAndEponent(I32): Indicates the I32 argument will contain bits to
specify the rounding mode. POWER also has bits
to specify the desired exponent. The s390
instructions only specify the rounding mode.
Summary of proposed Iops:
The references to D32, D64 and D128 indicate that the value in the floating
point register is a DFP value. The DFP instructions use the existing floating
point registers.
ARITHMETIC INSTRUCTIONS
-----------------------
IRRoundingMode(I32) X D64 X D64 -> D64
Iop_AddD64, Iop_SubD64, Iop_MulD64, Iop_DivD64
IRRoundingMode(I32) X D128 X D128 -> D128
Iop_AddD128, Iop_SubD128, Iop_MulD128, Iop_DivD128
FORMAT CONVERSION INSTRUCTIONS
------------------------------
InvOperationModes(I32) x D32 -> D64
Iop_D32toD64
InvOperationModes(I32) x D64 -> D128
Iop_D64toD128
IRRoundingExceptionModes(I32) x D64 -> D32
Iop_RoundD64toD32
IRRoundingExceptionModes(I32) x D128 -> D64
Iop_RoundD128toD64
IRRoundingExceptionModes(I32) x I64 -> D64
Iop_I64StoD64
IRRoundingExceptionModes(I32) x D64 -> I64
Iop_D64toI64
ROUNDING INSTRUCTIONS
-----------------------
IRRoundingMode(I32) x D64 -> D64
Iop_RoundD64
IRRoundingMode(I32) x D128 -> D128
Iop_RoundD128
COMPARE INSTRUCTIONS
-----------------------
D64 x D64 -> IRCmpF64Result(I32)
Iop_CmpD64
D128 x D128 -> IRCmpF64Result(I32)
Iop_CmpD128
D64 x D64 -> 1 if the condition is TRUE, 0 otherwise
Iop_CmpEQD64, Iop_CmpLTD64, Iop_CmpGTD64
D128 x D128 -> 1 if the condition is TRUE; 0 otherwise;
Iop_CmpEQD128, Iop_CmpLTD128, Iop_CmpGTD128
QUANTIZE AND ROUND INSTRUCTIONS
-------------------------------
IRRoundingMode(I32) x D64-> D64
Iop_QuantizeID64,
IRRoundingMode(I32) x D128-> D128
Iop_QuantizeID128
IRRoundingMode(I32) x D64 x D64 -> D64
Iop_QuantizeD64
IRRoundingMode(I32) x D128 x D128 -> D128
Iop_QuantizeD128
IRRoundingMode(I32) x D64 x D64 -> D64
Iop_SignificanceRoundD64
IRRoundingMode(I32) x D128 x D128 -> D128
Iop_SignificanceRoundD128
EXTRACT AND INSERT INSTRUCTIONS
-------------------------------
D64 -> I64
Iop_ExtractExpD64
D128 -> I64
Iop_ExtractExpD128
I64 x I64 -> D64
Iop_InsertExpD64
I64 x I128 -> D128
Iop_InsertExpD128
SHIFT SIGNIFICAND INSTRUCTIONS
-------------------------------
U16 x D64 -> D64
Iop_ShlD64, Iop_ShrD64
U16 x D128 -> D128
Iop_ShlD128, Iop_ShrD128
This section give the detailed mapping of Power and s390 instructions to the
proposed DFP Iops or how they would be implemented with the existing Iops and
the proposed DFP Iops.
ARITHMETIC INSTRUCTIONS
Iop s390 Power Description of instruction, implementation
opcode opcode details
-------------------------------------------------------------------------------
Iop_AddD64 IRRoundingMode(I32) X D64 X D64 -> D64
ADTR dadd
ADTRA Add two 64-bit DFP numbers. If both operands
are finite numbers, they are added
algebraically, forming an intermediate
sum. The intermediate sum, if nonzero, is
rounded to the operand format and the rounded
value is then placed at the result location.
The ADTRA instruction has a field to specify
the desired rounding mode but is otherwise
identical to the ADTR.
Iop_AddD128 IRRoundingMode(I32) X D128 X D128 -> D128
AXTR daddq
AXTRA Add two 128-bit DFP numbers If both operands
are finite numbers, they are added
algebraically, forming an intermediate sum. The
intermediate sum, if nonzero, is rounded to the
operand format and the rounded value is then
placed at the result location.
The AXTRA instruction has a field to specify
the desired rounding mode.
Iop_SubD64 IRRoundingMode(I32) X D64 X D64 -> D64
SDTR dsub
SDTRA
The execution of SUBTRACT is identical to that
of ADD, except that the second operand, if
numeric, participates in the operation with
its sign bit inverted.
The SXTRA instruction has a field to specify
the desired rounding mode but is otherwise
identical to the SDTR.
Iop_SubD128 IRRoundingMode(I32) X D128 X D128 -> D128
SXTR dsubq
SXTRA
The execution of SUBTRACT is identical to that
of ADD, except that the second operand, if
numeric, participates in the operation with
its sign bit inverted.
The SXTRA instruction has a field to specify
the desired rounding mode but is otherwise
identical to the SXTRA.
Iop_MulD64 IRRoundingMode(I32) X D64 X D64 -> D64
MDTR dmul
MDTRA
If both source operands are finite numbers,
they are multiplied to form an intermediate
product. The intermediate product is rounded
to the target format.
The MDTRA instruction has a field to specify
the desired rounding mode but is otherwise
identical to the MDTR.
Iop_MulD128 IRRoundingMode(I32) X D128 X D128 -> D128
MXTR dmulq
MXTRA
If both source operands are finite numbers,
they are multiplied to form an intermediate
product. The intermediate product is rounded
to the target format.
The MXTRA instruction has a field to specify
the desired rounding mode but is otherwise
identical to the MXTR.
Iop_DivD64 IRRoundingMode(I32) X D64 X D64 -> D64
DDTR ddiv
DDTRA
If divisor is nonzero and both the dividend and
divisor are finite numbers, the first operand
is divided by the second operand to form an
intermediate quotient. The intermediate
quotient, if nonzero, is rounded to the target
format.
The MDTRA instruction has a field to specify
the desired rounding mode but is otherwise
identical to the MDTR.
Iop_DivD128 IRRoundingMode(I32) X D128 X D128 -> D128
DXTR ddivq
DXTRA
If divisor is nonzero and both the dividend and
divisor are finite numbers, the first operand
is divided by the second operand to form an
intermediate quotient. The intermediate
quotient, if nonzero, is rounded to the target
format.
The DXTRA instruction has a field to specify
the desired rounding mode but is otherwise
identical to the MXTR.
FORMAT CONVERSION INSTRUCTIONS
Iop s390 Power Description of instruction, implementation
opcode opcode details
-------------------------------------------------------------------------------
TBD
PFPO
The PFPO instruction operation is specified by
the code in general purpose register 0 and the
condition code is set to indicate the result.
The operations that can be specified for this
instruction include a large list of format
conversions to/from various sizes of DFP
operands and various sizes of Hexadecimal
floating point and Binary floating point
formats.
Iop_D32toD64 InvOperationModes(I32) x D32 -> D64
LDETR dctdp
The 32-bit DFP source operand is converted into
a 64-bit DFP result. The I32 operand is for
specifying the IEEE invalid operation exception
control mode, if required.
Iop_D64toD128 InvOperationModes(I32) x x D64 -> D128
LXETR dctqpq
The 64-bit DFP source operand is
converted into a 128-bit DFP result. The I32
operand is for specifying the IEEE invalid
operation exception control mode, if required.
Iop_RoundD64toD32 IRRoundingExceptionModes(I32) x D64 -> D64
LEDTR drsp
The 64-bit DFP source operand is rounded to a
DFP 32-bit value, according to the rounding
mode.
Iop_RoundD128toD64 IRRoundingExceptionModes(I32) x D128 -> D64
LDXTR drdpq
The 128-bit DFP source operand is rounded,
according to the rounding mode.
Iop_I64StoD64 IRRoundingExceptionModes(I32) x I64 -> D64
CDGTR dcffix
CDGTRA
The 64-bit signed binary-integer in the second
source operand is converted into a 64-bit DFP
result using the rounding mode specified in
the first operand.
May need new Iop IRRoundingExceptionModes(I32) x D64 -> I64
TBD CLGDTR
The 64-bit DFP source operand is rounded to a
signed integer, according to the rounding mode
specified by the first operand, and converted
into a signed 64-bit binary integer result with
the same sign as the source.
Implementation: the 64-bit DFP source operand
is rounded into a 64-bit signed integer using
the existing instruction Iop_D64toI64.
CONCERN: HOW DO WE CONVERT FROM SIGNED INT TO
UNSIGNED INT?? IF WE DO THE CONVERSION
TO SIGNED THEN TO UNSIGNED WE LOSE
RANGE FOR AN UNSIGNED VALUE. IF USING
EXISTING IOPS IS NOT VIABLE, WILL
NEED A NEW IOP. TBD WHEN DFP SUPPORT
IS ADDED FOR S390.
May need new Iop IRRoundingExceptionModes(I32) x D64 -> I32
TBD CLFDTR
The 64-bit DFP source operand is rounded to a
signed integer, according to the rounding mode
specified by the first operand, and converted
into a signed 32-bit integer result with
the same sign as the source.
Implementation: the 64-bit DFP source operand
is rounded into a 64-bit signed integer using
the existing instruction Iop_D64toI64, then
Iop_64to32 convert to a signed 32-bit integer.
CONCERN: HOW DO WE CONVERT FROM SIGNED INT TO
UNSIGNED INT?? IF WE DO THE CONVERSION
TO SIGNED THEN TO UNSIGNED WE LOSE
RANGE FOR AN UNSIGNED VALUE. IF USING
EXISTING IOPS IS NOT VIABLE, WILL
NEED A NEW IOP. TBD WHEN DFP SUPPORT
IS ADDED FOR S390.
May need new Iop IRRoundingExceptionModes(I32) x D128 -> I64
TBD CLGXTR
The 128-bit DFP source operand is rounded to a
signed integer, according to the rounding mode
specified by the first operand, and converted
into a signed 64-bit integer result with
the same sign as the source.
Implementation: the 128-bit DFP source operand
is rounded into a 64-bit DFP with the
Iop_RoundD128toD64 instruction, 64-bit DFP is
rounded to a 64-bit signed integer using the
existing instruction Iop_D64toI64.
CONCERN: HOW DO WE CONVERT FROM SIGNED INT TO
UNSIGNED INT?? IF WE DO THE CONVERSION
TO SIGNED THEN TO UNSIGNED WE LOSE
RANGE FOR AN UNSIGNED VALUE. IF
USING EXISTING IOPS IS NOT VIABLE,
WILL NEED A NEW IOP. TBD WHEN DFP
SUPPORT IS ADDED FOR S390.
May need new Iop IRRoundingExceptionModes(I32) x D128 -> I32
TBD CLFXTR
The 128-bit DFP source operand is rounded to a
signed integer, according to the rounding mode
specified by the first operand, and converted
into a signed 32-bit integer result with
the same sign as the source.
Implementation: the 128-bit DFP source operand
is rounded into a 64-bit DFP with the
Iop_RoundD128toD64 instruction,the 64-bit DFP
is then converted to a 64-bit signed integer
using the existing instruction Iop_D64toI64,
then Iop_64to32 convert to a signed 32-bit
integer.
CONCERN: HOW DO WE CONVERT FROM SIGNED INT TO
UNSIGNED INT?? IF WE DO THE CONVERSION
TO SIGNED THEN TO UNSIGNED WE LOSE
RANGE FOR AN UNSIGNED VALUE. IF USING
EXISTING IOPS IS NOT VIABLE, WILL
NEED A NEW IOP. TBD WHEN DFP SUPPORT
IS ADDED FOR S390.
ROUNDING INSTRUCTIONS
Iop s390 Power Description of instruction, implementation
opcode opcode details
-------------------------------------------------------------------------------
Iop_RoundD64 IRRoundingMode(I32) x D64 -> D64
FIDTR drintx
The D64 operand, if a finite number, is rounded
to an integer value, with inexact.
The DFP operand is rounded and stored in the
floating point register as a binary integer
value based on the specified rounding mode and
stored as a DFP.
COMMNET: THE FIDTR INSTRUCTION HAS THE M3
FIELD FOR THE ROUNDING MODE. IT ALSO
HAS THE M4 FIELD WHICH APPEARS TO BE
UNUSED AT PRESENT. IN THE FUTURE,
THE I32 OPERAND COULD BE USED TO HOLD
BOTH M3 AND M4.
Iop_RoundD128 IRRoundingMode(I32) x D128 -> D128
FIXTR drintxq
The D128 operand, if a finite number, is
rounded to a binary integer value, with
inexact. The DFP operand is rounded and stored
in the floating point register as a binary
integer based on the specified rounding mode.
COMMNET: THE FIXTR INSTRUCTION HAS THE M3
FIELD FOR THE ROUNDING MODE. IT ALSO
HAS THE M4 FIELD WHICH APPEARS TO BE
UNUSED AT PRESENT. IN THE FUTURE,
THE I32 OPERAND COULD BE USED TO HOLD
BOTH M3 AND M4.
COMPARE INSTRUCTIONS
Iop s390 Power Description of instruction, implementation
opcode opcode details
-------------------------------------------------------------------------------
Iop_CmpD64 D64 x D64 -> IRCmpF64Result(I32)
dcmpo
dcmpu
Perform the comparison, as specified in the
instruction. The instruction sets the platform
condition codes. The condition codes for the
virtual machine need to be updated based on the
result in ths platform specific condition code
register.
Iop_CmpD128 D128 x D128 -> IRCmpF64Result(I32)
dcmpoq
dcmpuq
Perform the comparison, as specified in the
instruction. The instruction sets the platform
condition codes. The condition codes for the
virtual machine need to be updated based on the
result in ths platform specific condition code
register.
QUANTIZE AND ROUND INSTRUCTIONS
Iop s390 Power Description of instruction, implementation
opcode opcode details
-------------------------------------------------------------------------------
Iop_QuantizeID64 IRRoundingModeAndEponent(I32) x D64 -> D64
QADTR dquai
The D64 source operand is converted and rounded
to the form with the immediate exponent
specified by the rounding and exponent
parameter.
Iop_QuantizeID128 IRRoundingModeAndExponent(I32) x D128-> D128
QAXTR dquaiq
The D128 source operand is converted and
rounded to the form with the immediate exponent
specified by the rounding and exponent
parameter.
Iop_QuantizeD64 IRRoundingMode(I32) x D64 x D64 -> D64
dqua
The instruction second D64 operand is converted
and rounded to the form with the same exponent
as that of the first DFP operand. The result
is placed in the result opernad.
Note, s390 Does not have the immediate
quantize instruction. Hence can't emulate it
on s390 using the immediate instruction
Iop_QuantizeD128 IRRoundingMode(I32) x D128 x D128-> D128
dquaq
The instruction second D128 operand is
converted and rounded to the form with the same
exponent as that of the first DFP operand. The
result is placed in the result opernad.
Note, s390 Does not have the immediate
quantize instruction. Hence can't emulate it
on s390 using the immediate instruction
Iop_SignificanceRoundD64 IRRoundingMode(I32) x D64 x D64 -> D64
RRDTR drrnd
The D32 or D64 operand is rounded to the
requested significance given by the I8 operand
as specified by the rounding mode.
Iop_SignificanceRoundD128 IRRoundingMode(I32) x D128 x D128 -> D128
RRXTR drrndq
The D128 operand is rounded to the requested
significance given by the I8 operand as
specified by the rounding mode.
EXTRACT AND INSERT INSTRUCTIONS
Iop s390 Power Description of instruction, implementation
opcode opcode details
-------------------------------------------------------------------------------
TBD D64 -> I64
ESDTR
This Iop is only needed by s390. It will not
be used for Power and hence may need to be
added when s390 adds DFP support to Valgrind.
Final decision is left to s390 team.
The result is the number of DFP significant
digits of the D32 or D64 operand. The result
is a 64-bit signed value.
TBD D128 -> D644
ESXTR
This Iop is only needed by s390. It will not
be used for Power and hence may need to be
added when s390 adds DFP support to Valgrind.
Final decision is left to s390 team.
The result is the number of DFP significant
digits of the D32 operand. The result is
a 64-bit signed value.
Iop_ExtractExpD64 D64 -> I64
EEDTR dxex
The exponent of the D64 operand is extracted.
The extracted exponent is converted and stored
in the floating point register as a signed
64-bit binary integer format.
Iop_ExtractExpD128 D128 -> I64
EEXTR dxexq
The exponent of the D128 operand is extracted.
The extracted exponent is converted and stored
in the floating point register as a signed
64-bit binary integer.
Iop_InsertExpD64 I64 x I64 -> D64
IEDTR diex
The exponent is specified by the first I64
operand the signed significand is given by the
second I64 value. The result is a D64 value
consisting of the specified significand and
exponent whose sign is that of the specified
significand.
Iop_InsertExpD128 I64 x I128 -> D128
IEXTR diexq
The exponent is specified by the first I64
operand the signed significand is given by the
second I128 value. The result is a D128 value
consisting of the specified significand and
exponent whose sign is that of the specified
significand.
SHIFT SIGNIFICAND INSTRUCTIONS
Iop s390 Power Description of instruction, implementation
opcode opcode details
-------------------------------------------------------------------------------
Iop_ShlD64 U8 x D64 -> D64
SLDT dscli
The D32 or D64 significand is shifted left by
the number of digits specified by the U8
operand. Digits shifted out of the leftmost
digit are lost. Zeros are supplied to the
vacated positions on the right. The sign of
the result is the same as the sign of the D64
operand.
Iop_ShlD128 U8 x D128 -> D128
SLDT dscliq
The D128 significand is shifted left by the
number of digits specified by the U8 operand.
Digits shifted out of the leftmost digit are
lost. Zeros are supplied to the vacated
positions on the right. The sign of the result
is the same as the sign of the D128 operand.
Iop_ShrD64 U8 x D64 -> D64
SLDT dscri
The D32 or D64 significand is shifted right by
the number of digits specified by the U8
operand. Digits shifted out of the right most
digit are lost. Zeros are supplied to the
vacated positions on the left. The sign of the
result is the same as the sign of the D64
operand.
Iop_ShrD128 U8 x D128 -> D128
SLDT dscriq
The D128 significand is shifted right by the
number of digits specified by the U8 operand.
Digits shifted out of the right most digit are
lost. Zeros are supplied to the vacated
positions on the left. The sign of the result
is the same as the sign of the D128 operand.
Thank you for your time and consideration to review this proposal.
Carl Love
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