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From: Stephen M. <sm...@al...> - 2011-10-27 21:38:05
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>>>>> "JS" == svn <sv...@va...> writes:
JS> Author: sewardj
JS> Date: 2011-10-26 16:06:25 +0100 (Wed, 26 Oct 2011)
JS> New Revision: 2227
JS> Log:
JS> Handle "add.w reg, sp, #constT" and "addw reg, sp, #uimm12" for
JS> reg != PC. Previous handling was overly restrictive -- only
JS> allowed reg == SP. (n-i-bz)
Seeing this patch go by reminds me that I'd noticed a similar
seemingly incorrect set of constrains for the versions of the add.w
and sub.w instructions that take another register and an optional
shift rather than an immediate. I'm still working on an appropriate
test suite addition (it's slow going since I only have software
emulators).
If no-one besides me has run into it yet, I was guessing that my
change wasn't important enough to rush into 3.7, but I'm appending it
below in case anyone wants to take a look; it will be in Bugzilla in
the future.
-- Stephen
Index: priv/guest_arm_toIR.c
===================================================================
--- priv/guest_arm_toIR.c (revision 2228)
+++ priv/guest_arm_toIR.c (working copy)
@@ -16358,16 +16358,18 @@
UInt how = INSN1(5,4);
Bool valid = !isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM);
- /* but allow "add.w reg, sp, reg w/ no shift
+ /* but allow "add.w reg, sp, reg w/ lsl up to 3
(T3) "ADD (SP plus register) */
if (!valid && INSN0(8,5) == BITS4(1,0,0,0) // add
- && rD != 15 && rN == 13 && imm5 == 0 && how == 0) {
+ && rD != 15 && rN == 13 && rM != 13 && rM != 15
+ && imm5 <= 3 && how == 0) {
valid = True;
}
- /* also allow "sub.w reg, sp, reg w/ no shift
+ /* also allow "sub.w reg, sp, reg w/ lsl up to 3
(T1) "SUB (SP minus register) */
if (!valid && INSN0(8,5) == BITS4(1,1,0,1) // sub
- && rD != 15 && rN == 13 && imm5 == 0 && how == 0) {
+ && rD != 15 && rN == 13 && rM != 13 && rM != 15
+ && imm5 <= 3 && how == 0) {
valid = True;
}
if (valid) {
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