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From: Christian B. <bor...@de...> - 2011-08-07 19:50:45
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On 30/07/11 17:44, Florian Krohm wrote:
> On 07/30/2011 11:02 AM, Christian Borntraeger wrote:
>>>
>>> +vex s390->IR: unknown insn: 0000
>>> +vex s390->IR: unknown insn: 0000
>>> +vex s390->IR: unknown insn: 0000
>>> +vex s390->IR: unknown insn: 0000
>>> +vex: priv/guest_generic_bb_to_IR.c:327 (bb_to_IR): Assertion
>>> `dres.continueAt == 0' failed.
>>
>> Something else is wrong (of course it might be s390 code), but instruction
>> opcode 0 is guaranteed to be never used, so it is either a jump to a place
>> that does not contain code or some trap etc. that is supposed to fault. But
>> VEX does not need to handle 0000.
>>
>
> Right, this is just the symptom. The cause might be my change r2185 in
> VEX. I'm looking at that.
I found some time to look at the ex_clone testcase. The error comes from
decoding libcs abort function coming from base_from_cb_data
(which was not done before we had resteer)
[...]
3b7f6: e3 10 d0 00 00 12 lt %r1,0(%r13)
3b7fc: a7 84 00 e6 je 3b9c8 <abort+0x234>
3b800: a7 1e 00 01 chi %r1,1
3b804: a7 84 00 d5 je 3b9ae <abort+0x21a>
3b808: a7 1e 00 02 chi %r1,2
3b80c: a7 84 00 43 je 3b892 <abort+0xfe>
3b810: a7 1e 00 03 chi %r1,3
3b814: a7 84 00 a2 je 3b958 <abort+0x1c4>
3b818: a7 1e 00 04 chi %r1,4
3b81c: a7 84 00 30 je 3b87c <abort+0xe8>
3b820: a7 1e 00 05 chi %r1,5
3b824: a7 84 00 1f je 3b862 <abort+0xce>
3b828: a7 1e 00 06 chi %r1,6
3b82c: a7 84 00 11 je 3b84e <abort+0xba>
3b830: a7 1e 00 07 chi %r1,7
3b834: a7 84 00 0e je 3b850 <abort+0xbc>
3b838: 00 00 a7 f4 .long 0x0000a7f4
3b83c: ff ff c0 20 .long 0xffffc020
3b840: 00 0b bf 81 .long 0x000bbf81
[...]
the code in question is
[...]
if (stage == 7)
{
++stage;
_exit (127);
}
[...]
while (1)
/* Try for ever and ever. */
ABORT_INSTRUCTION;
and ABORT_INSTRUCTION is defined as
"asm (".word 0")"
Florian, looks like we should treat 0000 special.
Christian
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