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From: <sv...@va...> - 2010-09-22 00:59:02
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Author: sewardj
Date: 2010-09-22 01:58:51 +0100 (Wed, 22 Sep 2010)
New Revision: 11371
Log:
Handle new 32-bit SIMD integer primops introduced in vex r2037.
Modified:
trunk/memcheck/mc_translate.c
Modified: trunk/memcheck/mc_translate.c
===================================================================
--- trunk/memcheck/mc_translate.c 2010-09-21 09:05:20 UTC (rev 11370)
+++ trunk/memcheck/mc_translate.c 2010-09-22 00:58:51 UTC (rev 11371)
@@ -1724,7 +1724,17 @@
return assignNew('V', mce, Ity_I64, unop(Iop_CmpNEZ8x8, at));
}
+static IRAtom* mkPCast16x2 ( MCEnv* mce, IRAtom* at )
+{
+ return assignNew('V', mce, Ity_I32, unop(Iop_CmpNEZ16x2, at));
+}
+static IRAtom* mkPCast8x4 ( MCEnv* mce, IRAtom* at )
+{
+ return assignNew('V', mce, Ity_I32, unop(Iop_CmpNEZ8x4, at));
+}
+
+
/* Here's a simple scheme capable of handling ops derived from SSE1
code and while only generating ops that can be efficiently
implemented in SSE1. */
@@ -2071,7 +2081,27 @@
return at;
}
+/* --- 32-bit versions --- */
+static
+IRAtom* binary8Ix4 ( MCEnv* mce, IRAtom* vatom1, IRAtom* vatom2 )
+{
+ IRAtom* at;
+ at = mkUifU32(mce, vatom1, vatom2);
+ at = mkPCast8x4(mce, at);
+ return at;
+}
+
+static
+IRAtom* binary16Ix2 ( MCEnv* mce, IRAtom* vatom1, IRAtom* vatom2 )
+{
+ IRAtom* at;
+ at = mkUifU32(mce, vatom1, vatom2);
+ at = mkPCast16x2(mce, at);
+ return at;
+}
+
+
/*------------------------------------------------------------*/
/*--- Generate shadow values from all kinds of IRExprs. ---*/
/*------------------------------------------------------------*/
@@ -2197,6 +2227,30 @@
tl_assert(sameKindedAtoms(atom2,vatom2));
switch (op) {
+ /* 32-bit SIMD */
+
+ case Iop_Add16x2:
+ case Iop_HAdd16Ux2:
+ case Iop_HAdd16Sx2:
+ case Iop_Sub16x2:
+ case Iop_HSub16Ux2:
+ case Iop_HSub16Sx2:
+ case Iop_QAdd16Sx2:
+ case Iop_QSub16Sx2:
+ return binary16Ix2(mce, vatom1, vatom2);
+
+ case Iop_Add8x4:
+ case Iop_HAdd8Ux4:
+ case Iop_HAdd8Sx4:
+ case Iop_Sub8x4:
+ case Iop_HSub8Ux4:
+ case Iop_HSub8Sx4:
+ case Iop_QSub8Ux4:
+ case Iop_QAdd8Ux4:
+ case Iop_QSub8Sx4:
+ case Iop_QAdd8Sx4:
+ return binary8Ix4(mce, vatom1, vatom2);
+
/* 64-bit SIMD */
case Iop_ShrN8x8:
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