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From: <sv...@va...> - 2010-09-01 10:26:00
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Author: sewardj
Date: 2010-09-01 11:25:51 +0100 (Wed, 01 Sep 2010)
New Revision: 2025
Log:
Avoid genSpill/genReload asserts for VFP spills/reloads with offsets
greater than 1024 from the baseblock pointer.
Also, update comments on the use of r12.
Modified:
trunk/priv/host_arm_defs.c
Modified: trunk/priv/host_arm_defs.c
===================================================================
--- trunk/priv/host_arm_defs.c 2010-08-31 09:32:40 UTC (rev 2024)
+++ trunk/priv/host_arm_defs.c 2010-09-01 10:25:51 UTC (rev 2025)
@@ -160,14 +160,15 @@
//(*arr)[i++] = hregARM_Q15();
// unavail: r8 as GSP
- // r12 'cos we're not sure what it's for
+ // r12 is used as a spill/reload temporary
// r13 as SP
// r14 as LR
// r15 as PC
//
// All in all, we have 11 allocatable integer registers:
- // 0 1 2 3 4 5 6 7 9 10 11 plus r8 dedicated as GSP.
- // 12 13 14 and 15 are not under the allocator's control.
+ // 0 1 2 3 4 5 6 7 9 10 11, with r8 dedicated as GSP
+ // and r12 dedicated as a spill temporary.
+ // 13 14 and 15 are not under the allocator's control.
//
// Hence for the allocatable registers we have:
//
@@ -2371,9 +2372,11 @@
HReg base = r8;
vassert(0 == (offsetB & 3));
if (offsetB >= 1024) {
+ Int offsetKB = offsetB / 1024;
+ /* r12 = r8 + (1024 * offsetKB) */
*i1 = ARMInstr_Alu(ARMalu_ADD, r12, r8,
- ARMRI84_I84(1,11)); /* 1024 */
- offsetB -= 1024;
+ ARMRI84_I84(offsetKB, 11));
+ offsetB -= (1024 * offsetKB);
base = r12;
}
vassert(offsetB <= 1020);
@@ -2424,9 +2427,11 @@
HReg base = r8;
vassert(0 == (offsetB & 3));
if (offsetB >= 1024) {
+ Int offsetKB = offsetB / 1024;
+ /* r12 = r8 + (1024 * offsetKB) */
*i1 = ARMInstr_Alu(ARMalu_ADD, r12, r8,
- ARMRI84_I84(1,11)); /* 1024 */
- offsetB -= 1024;
+ ARMRI84_I84(offsetKB, 11));
+ offsetB -= (1024 * offsetKB);
base = r12;
}
vassert(offsetB <= 1020);
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