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From: <sv...@va...> - 2010-08-06 08:01:56
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Author: sewardj
Date: 2010-08-06 09:01:47 +0100 (Fri, 06 Aug 2010)
New Revision: 11249
Log:
Track vex r2001 (initial PCMPISTRI support):
* handle new pseudo-reg XMM16 in memcheck/mc_machine.c
* run_thread_for_a_while: assert that the amd64 XMM guest reg array
has no holes and the elements are the right size, so that the
(PCMP)ISTRI_* helpers can treat it as an array.
Modified:
trunk/coregrind/m_scheduler/scheduler.c
trunk/memcheck/mc_machine.c
Modified: trunk/coregrind/m_scheduler/scheduler.c
===================================================================
--- trunk/coregrind/m_scheduler/scheduler.c 2010-07-31 13:37:58 UTC (rev 11248)
+++ trunk/coregrind/m_scheduler/scheduler.c 2010-08-06 08:01:47 UTC (rev 11249)
@@ -644,6 +644,16 @@
vg_assert(sz_spill == LibVEX_N_SPILL_BYTES);
vg_assert(a_vex + 3 * sz_vex == a_spill);
+# if defined(VGA_amd64)
+ /* x86/amd64 XMM regs must form an array, ie, have no
+ holes in between. */
+ vg_assert(
+ (offsetof(VexGuestAMD64State,guest_XMM16)
+ - offsetof(VexGuestAMD64State,guest_XMM0))
+ == (17/*#regs*/-1) * 16/*bytes per reg*/
+ );
+# endif
+
# if defined(VGA_ppc32) || defined(VGA_ppc64)
/* ppc guest_state vector regs must be 16 byte aligned for
loads/stores. This is important! */
@@ -654,7 +664,7 @@
vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex.guest_VR1));
vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow1.guest_VR1));
vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow2.guest_VR1));
-# endif
+# endif
# if defined(VGA_arm)
/* arm guest_state VFP regs must be 8 byte aligned for
Modified: trunk/memcheck/mc_machine.c
===================================================================
--- trunk/memcheck/mc_machine.c 2010-07-31 13:37:58 UTC (rev 11248)
+++ trunk/memcheck/mc_machine.c 2010-08-06 08:01:47 UTC (rev 11249)
@@ -536,6 +536,7 @@
if (o >= GOF(XMM13) && o+sz <= GOF(XMM13)+SZB(XMM13)) return GOF(XMM13);
if (o >= GOF(XMM14) && o+sz <= GOF(XMM14)+SZB(XMM14)) return GOF(XMM14);
if (o >= GOF(XMM15) && o+sz <= GOF(XMM15)+SZB(XMM15)) return GOF(XMM15);
+ if (o >= GOF(XMM16) && o+sz <= GOF(XMM16)+SZB(XMM16)) return GOF(XMM16);
/* MMX accesses to FP regs. Need to allow for 32-bit references
due to dirty helpers for frstor etc, which reference the entire
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