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From: <sv...@va...> - 2009-12-31 19:26:18
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Author: sewardj
Date: 2009-12-31 19:26:03 +0000 (Thu, 31 Dec 2009)
New Revision: 1950
Log:
Make the x86 and amd64 back ends use the revised prototypes for
genSpill and genReload. ppc32/64 backends are still broken.
Also, tidy up associated pointer-type casting in main_main.c.
Modified:
trunk/priv/host_amd64_defs.c
trunk/priv/host_amd64_defs.h
trunk/priv/host_x86_defs.c
trunk/priv/host_x86_defs.h
trunk/priv/main_main.c
Modified: trunk/priv/host_amd64_defs.c
===================================================================
--- trunk/priv/host_amd64_defs.c 2009-12-31 18:00:12 UTC (rev 1949)
+++ trunk/priv/host_amd64_defs.c 2009-12-31 19:26:03 UTC (rev 1950)
@@ -1912,37 +1912,44 @@
register allocator. Note it's critical these don't write the
condition codes. */
-AMD64Instr* genSpill_AMD64 ( HReg rreg, Int offsetB, Bool mode64 )
+void genSpill_AMD64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
+ HReg rreg, Int offsetB, Bool mode64 )
{
AMD64AMode* am;
vassert(offsetB >= 0);
vassert(!hregIsVirtual(rreg));
vassert(mode64 == True);
+ *i1 = *i2 = NULL;
am = AMD64AMode_IR(offsetB, hregAMD64_RBP());
-
switch (hregClass(rreg)) {
case HRcInt64:
- return AMD64Instr_Alu64M ( Aalu_MOV, AMD64RI_Reg(rreg), am );
+ *i1 = AMD64Instr_Alu64M ( Aalu_MOV, AMD64RI_Reg(rreg), am );
+ return;
case HRcVec128:
- return AMD64Instr_SseLdSt ( False/*store*/, 16, rreg, am );
+ *i1 = AMD64Instr_SseLdSt ( False/*store*/, 16, rreg, am );
+ return;
default:
ppHRegClass(hregClass(rreg));
vpanic("genSpill_AMD64: unimplemented regclass");
}
}
-AMD64Instr* genReload_AMD64 ( HReg rreg, Int offsetB, Bool mode64 )
+void genReload_AMD64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
+ HReg rreg, Int offsetB, Bool mode64 )
{
AMD64AMode* am;
vassert(offsetB >= 0);
vassert(!hregIsVirtual(rreg));
vassert(mode64 == True);
+ *i1 = *i2 = NULL;
am = AMD64AMode_IR(offsetB, hregAMD64_RBP());
switch (hregClass(rreg)) {
case HRcInt64:
- return AMD64Instr_Alu64R ( Aalu_MOV, AMD64RMI_Mem(am), rreg );
+ *i1 = AMD64Instr_Alu64R ( Aalu_MOV, AMD64RMI_Mem(am), rreg );
+ return;
case HRcVec128:
- return AMD64Instr_SseLdSt ( True/*load*/, 16, rreg, am );
+ *i1 = AMD64Instr_SseLdSt ( True/*load*/, 16, rreg, am );
+ return;
default:
ppHRegClass(hregClass(rreg));
vpanic("genReload_AMD64: unimplemented regclass");
Modified: trunk/priv/host_amd64_defs.h
===================================================================
--- trunk/priv/host_amd64_defs.h 2009-12-31 18:00:12 UTC (rev 1949)
+++ trunk/priv/host_amd64_defs.h 2009-12-31 19:26:03 UTC (rev 1950)
@@ -744,8 +744,12 @@
extern Bool isMove_AMD64Instr ( AMD64Instr*, HReg*, HReg* );
extern Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr*,
Bool, void* dispatch );
-extern AMD64Instr* genSpill_AMD64 ( HReg rreg, Int offset, Bool );
-extern AMD64Instr* genReload_AMD64 ( HReg rreg, Int offset, Bool );
+
+extern void genSpill_AMD64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
+ HReg rreg, Int offset, Bool );
+extern void genReload_AMD64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
+ HReg rreg, Int offset, Bool );
+
extern void getAllocableRegs_AMD64 ( Int*, HReg** );
extern HInstrArray* iselSB_AMD64 ( IRSB*, VexArch,
VexArchInfo*,
Modified: trunk/priv/host_x86_defs.c
===================================================================
--- trunk/priv/host_x86_defs.c 2009-12-31 18:00:12 UTC (rev 1949)
+++ trunk/priv/host_x86_defs.c 2009-12-31 19:26:03 UTC (rev 1950)
@@ -1620,41 +1620,50 @@
register allocator. Note it's critical these don't write the
condition codes. */
-X86Instr* genSpill_X86 ( HReg rreg, Int offsetB, Bool mode64 )
+void genSpill_X86 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
+ HReg rreg, Int offsetB, Bool mode64 )
{
X86AMode* am;
vassert(offsetB >= 0);
vassert(!hregIsVirtual(rreg));
vassert(mode64 == False);
+ *i1 = *i2 = NULL;
am = X86AMode_IR(offsetB, hregX86_EBP());
-
switch (hregClass(rreg)) {
case HRcInt32:
- return X86Instr_Alu32M ( Xalu_MOV, X86RI_Reg(rreg), am );
+ *i1 = X86Instr_Alu32M ( Xalu_MOV, X86RI_Reg(rreg), am );
+ return;
case HRcFlt64:
- return X86Instr_FpLdSt ( False/*store*/, 10, rreg, am );
+ *i1 = X86Instr_FpLdSt ( False/*store*/, 10, rreg, am );
+ return;
case HRcVec128:
- return X86Instr_SseLdSt ( False/*store*/, rreg, am );
+ *i1 = X86Instr_SseLdSt ( False/*store*/, rreg, am );
+ return;
default:
ppHRegClass(hregClass(rreg));
vpanic("genSpill_X86: unimplemented regclass");
}
}
-X86Instr* genReload_X86 ( HReg rreg, Int offsetB, Bool mode64 )
+void genReload_X86 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
+ HReg rreg, Int offsetB, Bool mode64 )
{
X86AMode* am;
vassert(offsetB >= 0);
vassert(!hregIsVirtual(rreg));
vassert(mode64 == False);
+ *i1 = *i2 = NULL;
am = X86AMode_IR(offsetB, hregX86_EBP());
switch (hregClass(rreg)) {
case HRcInt32:
- return X86Instr_Alu32R ( Xalu_MOV, X86RMI_Mem(am), rreg );
+ *i1 = X86Instr_Alu32R ( Xalu_MOV, X86RMI_Mem(am), rreg );
+ return;
case HRcFlt64:
- return X86Instr_FpLdSt ( True/*load*/, 10, rreg, am );
+ *i1 = X86Instr_FpLdSt ( True/*load*/, 10, rreg, am );
+ return;
case HRcVec128:
- return X86Instr_SseLdSt ( True/*load*/, rreg, am );
+ *i1 = X86Instr_SseLdSt ( True/*load*/, rreg, am );
+ return;
default:
ppHRegClass(hregClass(rreg));
vpanic("genReload_X86: unimplemented regclass");
Modified: trunk/priv/host_x86_defs.h
===================================================================
--- trunk/priv/host_x86_defs.h 2009-12-31 18:00:12 UTC (rev 1949)
+++ trunk/priv/host_x86_defs.h 2009-12-31 19:26:03 UTC (rev 1950)
@@ -685,8 +685,12 @@
extern Bool isMove_X86Instr ( X86Instr*, HReg*, HReg* );
extern Int emit_X86Instr ( UChar* buf, Int nbuf, X86Instr*,
Bool, void* dispatch );
-extern X86Instr* genSpill_X86 ( HReg rreg, Int offset, Bool );
-extern X86Instr* genReload_X86 ( HReg rreg, Int offset, Bool );
+
+extern void genSpill_X86 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
+ HReg rreg, Int offset, Bool );
+extern void genReload_X86 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
+ HReg rreg, Int offset, Bool );
+
extern X86Instr* directReload_X86 ( X86Instr* i,
HReg vreg, Short spill_off );
extern void getAllocableRegs_X86 ( Int*, HReg** );
Modified: trunk/priv/main_main.c
===================================================================
--- trunk/priv/main_main.c 2009-12-31 18:00:12 UTC (rev 1949)
+++ trunk/priv/main_main.c 2009-12-31 19:26:03 UTC (rev 1950)
@@ -243,10 +243,13 @@
getAllocableRegs_X86 ( &n_available_real_regs,
&available_real_regs );
isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_X86Instr;
- getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_X86Instr;
+ getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool))
+ getRegUsage_X86Instr;
mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_X86Instr;
- genSpill = (HInstr*(*)(HReg,Int, Bool)) genSpill_X86;
- genReload = (HInstr*(*)(HReg,Int, Bool)) genReload_X86;
+ genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool))
+ genSpill_X86;
+ genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool))
+ genReload_X86;
directReload = (HInstr*(*)(HInstr*,HReg,Short)) directReload_X86;
ppInstr = (void(*)(HInstr*, Bool)) ppX86Instr;
ppReg = (void(*)(HReg)) ppHRegX86;
@@ -263,10 +266,13 @@
getAllocableRegs_AMD64 ( &n_available_real_regs,
&available_real_regs );
isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_AMD64Instr;
- getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_AMD64Instr;
+ getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool))
+ getRegUsage_AMD64Instr;
mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_AMD64Instr;
- genSpill = (HInstr*(*)(HReg,Int, Bool)) genSpill_AMD64;
- genReload = (HInstr*(*)(HReg,Int, Bool)) genReload_AMD64;
+ genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool))
+ genSpill_AMD64;
+ genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool))
+ genReload_AMD64;
ppInstr = (void(*)(HInstr*, Bool)) ppAMD64Instr;
ppReg = (void(*)(HReg)) ppHRegAMD64;
iselSB = iselSB_AMD64;
@@ -284,8 +290,8 @@
isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPCInstr;
getRegUsage = (void(*)(HRegUsage*,HInstr*,Bool)) getRegUsage_PPCInstr;
mapRegs = (void(*)(HRegRemap*,HInstr*,Bool)) mapRegs_PPCInstr;
- genSpill = (HInstr*(*)(HReg,Int,Bool)) genSpill_PPC;
- genReload = (HInstr*(*)(HReg,Int,Bool)) genReload_PPC;
+ genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_PPC;
+ genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_PPC;
ppInstr = (void(*)(HInstr*,Bool)) ppPPCInstr;
ppReg = (void(*)(HReg)) ppHRegPPC;
iselSB = iselSB_PPC;
@@ -303,8 +309,8 @@
isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPCInstr;
getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_PPCInstr;
mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_PPCInstr;
- genSpill = (HInstr*(*)(HReg,Int, Bool)) genSpill_PPC;
- genReload = (HInstr*(*)(HReg,Int, Bool)) genReload_PPC;
+ genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_PPC;
+ genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_PPC;
ppInstr = (void(*)(HInstr*, Bool)) ppPPCInstr;
ppReg = (void(*)(HReg)) ppHRegPPC;
iselSB = iselSB_PPC;
@@ -316,18 +322,18 @@
break;
case VexArchARM:
- mode64 = False;
+ mode64 = False;
getAllocableRegs_ARM ( &n_available_real_regs,
&available_real_regs );
- isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_ARMInstr;
- getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_ARMInstr;
- mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_ARMInstr;
- genSpill = (HInstr*(*)(HReg,Int, Bool)) genSpill_ARM;
- genReload = (HInstr*(*)(HReg,Int, Bool)) genReload_ARM;
- ppInstr = (void(*)(HInstr*, Bool)) ppARMInstr;
- ppReg = (void(*)(HReg)) ppHRegARM;
- iselSB = iselSB_ARM;
- emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_ARMInstr;
+ isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_ARMInstr;
+ getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_ARMInstr;
+ mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_ARMInstr;
+ genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genSpill_ARM;
+ genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) genReload_ARM;
+ ppInstr = (void(*)(HInstr*, Bool)) ppARMInstr;
+ ppReg = (void(*)(HReg)) ppHRegARM;
+ iselSB = iselSB_ARM;
+ emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_ARMInstr;
host_is_bigendian = False;
host_word_type = Ity_I32;
vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_host.hwcaps));
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