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From: <sv...@va...> - 2009-12-29 17:00:50
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Author: sewardj
Date: 2009-12-29 17:00:33 +0000 (Tue, 29 Dec 2009)
New Revision: 10973
Log:
Remove special handling for the ARM commpage 0xFFFF0FE0 (get-the-TLS)
entry point, and instead use VEX-side support for the CP15 TPIDRURO
register for the same purpose. This allows us to run at least the
0xFFFF0FE0 commpage entry directly (on the simulated CPU).
Modified:
branches/ARM/coregrind/m_scheduler/scheduler.c
branches/ARM/coregrind/m_syswrap/syswrap-arm-linux.c
branches/ARM/coregrind/pub_core_threadstate.h
Modified: branches/ARM/coregrind/m_scheduler/scheduler.c
===================================================================
--- branches/ARM/coregrind/m_scheduler/scheduler.c 2009-12-29 16:56:18 UTC (rev 10972)
+++ branches/ARM/coregrind/m_scheduler/scheduler.c 2009-12-29 17:00:33 UTC (rev 10973)
@@ -1060,22 +1060,6 @@
vg_assert(trc != VEX_TRC_JMP_NOREDIR);
}
-# if defined(VGP_arm_linux)
- /* This is a dirty, dirty hack. When a program jumps to the
- location 0xFFFF0FE0 on linux, it's trying to read the
- TLS. The reason we're able to put the check here is because
- the fast cache will always miss when jumping to 0xFFFF0FE0
- because it gets trapped here. The check could go in the
- dispatcher, but ideally we can keep the check out of the fast
- path.
- */
- if (VG_(get_IP)(tid) == 0xFFFF0FE0) {
- trc = VG_TRC_BORING;
- VG_(set_IP)(tid, VG_(threads)[tid].arch.vex.guest_R14);
- VG_(threads)[tid].arch.vex.guest_R0 = VG_(threads)[tid].os_state.tls_addr;
- }
-# endif
-
switch (trc) {
case VG_TRC_BORING:
/* no special event, just keep going. */
Modified: branches/ARM/coregrind/m_syswrap/syswrap-arm-linux.c
===================================================================
--- branches/ARM/coregrind/m_syswrap/syswrap-arm-linux.c 2009-12-29 16:56:18 UTC (rev 10972)
+++ branches/ARM/coregrind/m_syswrap/syswrap-arm-linux.c 2009-12-29 17:00:33 UTC (rev 10973)
@@ -265,8 +265,9 @@
child->vex_shadow2 = parent->vex_shadow2;
}
-static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr ){
- VG_(threads)[tid].os_state.tls_addr = tlsptr;
+static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr )
+{
+ VG_(threads)[tid].arch.vex.guest_TPIDRURO = tlsptr;
return VG_(mk_SysRes_Success)( 0 );
}
Modified: branches/ARM/coregrind/pub_core_threadstate.h
===================================================================
--- branches/ARM/coregrind/pub_core_threadstate.h 2009-12-29 16:56:18 UTC (rev 10972)
+++ branches/ARM/coregrind/pub_core_threadstate.h 2009-12-29 17:00:33 UTC (rev 10973)
@@ -152,19 +152,6 @@
/* Initial state is False, False, Canc_Normal. */
# endif
-# if defined(VGP_arm_linux)
- // jrs: this seems like a hack. None of the other linux ports
- // have this. Do we really need it?
- // maybe needs to go in vex, a la x86 ldt/gdt pointer?
- Addr tls_addr;
- // The location that linux on ARM puts the TLS is
- // determined by what's in the commpage. Instead of
- // switching valgrind's TLS with the syscall on each
- // context switch (kinda expensive), we can just do our
- // own syscall to set the TLS, and trap accesses to the
- // commpage.
-# endif
-
# if defined(VGO_darwin)
// Mach trap POST handler as chosen by PRE
void (*post_mach_trap_fn)(ThreadId tid,
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