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From: Nicholas N. <n.n...@gm...> - 2009-11-09 01:49:30
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On Mon, Nov 9, 2009 at 4:34 AM, Julian Seward <js...@ac...> wrote: >> >> Is there a missunderstanding by me? > > Yes. It is true that 7.8% of references presented to the L2 cache miss > (7.8% == 13820 / 176349). > > The L2i miss rate tells you the proportion of instruction > reads that missed L2, == 2728 / 55537351 == 0.0% as it says. > > Similarly for the L2d miss rate. And the docs (http://www.valgrind.org/docs/manual/cg-manual.html, section 5.2.1) make this quite clear: "Note that the L2 miss rate is computed relative to the total number of memory accesses, not the number of L1 misses. I.e. it is (I2mr + D2mr + D2mw) / (Ir + Dr + Dw) not (I2mr + D2mr + D2mw) / (I1mr + D1mr + D1mw)" Nick |