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From: Josef W. <Jos...@gm...> - 2009-09-07 15:32:44
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On Saturday 29 August 2009, Tom Hughes wrote: > On 29/08/09 00:25, Julian Seward wrote: > > On Saturday 29 August 2009 01:19:45 am Nicholas Nethercote wrote: > > > >>> Log: > >>> Add support for the L2 cache on Intel T4200. > >> > >> Presumably callgrind should get this change too. > > > > Yes it definitely should. I thought (had assumed) that Callgrind and > > Cachegrind share the same cache detection code. Is that not the case? > > I believe they were separate but it looks like they were merged as > callgrind is now pulling in the code from cachegrind. As far as I remember, Callgrind (since its merge) always pulled in the detection of cache parameters from Cachegrind, as this was nicely separated from the rest of the code. Just a remark about the comment... AFAIK, the term "sectored" means on Intel processors a simple kind of hardware prefetching, where memory is partitioned into "sectors" consisting of 2 adjacent memory blocks the size of a cache line. When one memory block of a sector is fetched into the cache because of a load instruction, the other memory block of the sector is prefetched. This is a very simple stream prefetching heuristic, both for upwards and downwards streams. This has the consequence that for code doing sequential load accesses, it looks like the cache has a line size of 128 byte (instead of the real 64 byte), also when looking at performance counters. Please correct me if I am wrong... Josef > > Tom > |