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From: <sv...@va...> - 2009-08-28 22:34:23
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Author: sewardj Date: 2009-08-28 23:34:09 +0100 (Fri, 28 Aug 2009) New Revision: 10878 Log: Add support for the L2 cache on Intel T4200. Modified: trunk/cachegrind/cg-x86-amd64.c Modified: trunk/cachegrind/cg-x86-amd64.c =================================================================== --- trunk/cachegrind/cg-x86-amd64.c 2009-08-28 16:25:20 UTC (rev 10877) +++ trunk/cachegrind/cg-x86-amd64.c 2009-08-28 22:34:09 UTC (rev 10878) @@ -38,7 +38,7 @@ #include "cg_arch.h" -// All CPUID info taken from sandpile.org/a32/cpuid.htm */ +// All CPUID info taken from sandpile.org/ia32/cpuid.htm */ // Probably only works for Intel and AMD chips, and probably only for some of // them. @@ -174,6 +174,9 @@ micro_ops_warn(32, 32, 32); break; + /* not sectored, whatever that might mean */ + case 0x78: *L2c = (cache_t) { 1024, 4, 64 }; L2_found = True; break; + /* These are sectored, whatever that means */ case 0x79: *L2c = (cache_t) { 128, 8, 64 }; L2_found = True; break; case 0x7a: *L2c = (cache_t) { 256, 8, 64 }; L2_found = True; break; |