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From: <sv...@va...> - 2009-05-22 22:11:15
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Author: sewardj
Date: 2009-05-22 23:11:04 +0100 (Fri, 22 May 2009)
New Revision: 10117
Log:
Handle instrumentation of IRCAS (singleword only); just treat it as a
read. Which I think amounts to exactly the same as what happened
before IRCAS was introduced.
Modified:
branches/DCAS/helgrind/hg_main.c
Modified: branches/DCAS/helgrind/hg_main.c
===================================================================
--- branches/DCAS/helgrind/hg_main.c 2009-05-22 22:02:28 UTC (rev 10116)
+++ branches/DCAS/helgrind/hg_main.c 2009-05-22 22:11:04 UTC (rev 10117)
@@ -3642,10 +3642,11 @@
VexGuestExtents* vge,
IRType gWordTy, IRType hWordTy )
{
- Int i;
- IRSB* bbOut;
- Bool x86busLocked = False;
- Bool isSnoopedStore = False;
+ Int i;
+ IRSB* bbOut;
+ Bool isSnoopedStore = False;
+ Addr64 cia; /* address of current insn */
+ IRStmt* st;
if (gWordTy != hWordTy) {
/* We don't currently support this case. */
@@ -3665,8 +3666,16 @@
i++;
}
+ // Get the first statement, and initial cia from it
+ tl_assert(bbIn->stmts_used > 0);
+ tl_assert(i < bbIn->stmts_used);
+ st = bbIn->stmts[i];
+ tl_assert(Ist_IMark == st->tag);
+ cia = st->Ist.IMark.addr;
+ st = NULL;
+
for (/*use current i*/; i < bbIn->stmts_used; i++) {
- IRStmt* st = bbIn->stmts[i];
+ st = bbIn->stmts[i];
tl_assert(st);
tl_assert(isFlatIRStmt(st));
switch (st->tag) {
@@ -3674,11 +3683,15 @@
case Ist_AbiHint:
case Ist_Put:
case Ist_PutI:
- case Ist_IMark:
case Ist_Exit:
/* None of these can contain any memory references. */
break;
+ case Ist_IMark:
+ /* no mem refs, but note the insn address. */
+ cia = st->Ist.IMark.addr;
+ break;
+
case Ist_MBE:
//instrument_memory_bus_event( bbOut, st->Ist.MBE.event );
switch (st->Ist.MBE.event) {
@@ -3687,12 +3700,8 @@
/* Imbe_Bus{Lock,Unlock} arise from x86/amd64 LOCK
prefixed instructions. */
case Imbe_BusLock:
- tl_assert(x86busLocked == False);
- x86busLocked = True;
break;
case Imbe_BusUnlock:
- tl_assert(x86busLocked == True);
- x86busLocked = False;
break;
/* Imbe_SnoopedStore{Begin,End} arise from ppc
stwcx. instructions. */
@@ -3709,8 +3718,26 @@
}
break;
+ case Ist_CAS: {
+ /* Atomic read-modify-write cycle. Just pretend it's a
+ read. */
+ IRCAS* cas = st->Ist.CAS.details;
+ tl_assert(!isSnoopedStore);
+ /* FIXME: handle DCAS ! */
+ if (cas->oldHi != IRTemp_INVALID || cas->expdHi || cas->dataHi)
+ goto unhandled;
+ instrument_mem_access(
+ bbOut,
+ cas->addr,
+ sizeofIRType(typeOfIRExpr(bbIn->tyenv, cas->dataLo)),
+ False/*!isStore*/,
+ sizeofIRType(hWordTy)
+ );
+ break;
+ }
+
case Ist_Store:
- if (!x86busLocked && !isSnoopedStore)
+ if (!isSnoopedStore)
instrument_mem_access(
bbOut,
st->Ist.Store.addr,
@@ -3751,7 +3778,7 @@
}
/* This isn't really correct. Really the
instrumentation should be only added when
- (!x86busLocked && !isSnoopedStore), just like with
+ !isSnoopedStore, just like with
Ist_Store. Still, I don't think this is
particularly important. */
if (d->mFx == Ifx_Write || d->mFx == Ifx_Modify) {
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