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From: <sv...@va...> - 2009-05-21 21:44:44
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Author: sewardj
Date: 2009-05-21 22:44:38 +0100 (Thu, 21 May 2009)
New Revision: 1894
Log:
Add a new capabilities bit for AMD64, indicating whether or not
cmpxchg16b is support. Up till now we've been able to get away with
ignoring the question of whether the host can do cmpxchg16b. But not
any more; with double-word IRCAS with 64-bit words, we'll have to
generate a real cmpxchg16b insn at the back end. So we can't allow
cmpxchg16b in the front end in this case.
Modified:
branches/DCAS/pub/libvex.h
Modified: branches/DCAS/pub/libvex.h
===================================================================
--- branches/DCAS/pub/libvex.h 2009-05-21 21:40:21 UTC (rev 1893)
+++ branches/DCAS/pub/libvex.h 2009-05-21 21:44:38 UTC (rev 1894)
@@ -78,25 +78,28 @@
but not SSE1). LibVEX_Translate will check for nonsensical
combinations. */
-/* x86: baseline capability is Pentium-1 (FPU, MMX, but no SSE) */
+/* x86: baseline capability is Pentium-1 (FPU, MMX, but no SSE), with
+ cmpxchg8b. */
#define VEX_HWCAPS_X86_SSE1 (1<<1) /* SSE1 support (Pentium III) */
#define VEX_HWCAPS_X86_SSE2 (1<<2) /* SSE2 support (Pentium 4) */
#define VEX_HWCAPS_X86_SSE3 (1<<3) /* SSE3 support (>= Prescott) */
-/* amd64: baseline capability is SSE2 */
+/* amd64: baseline capability is SSE2, with cmpxchg8b but not
+ cmpxchg16b. */
#define VEX_HWCAPS_AMD64_SSE3 (1<<4) /* SSE3 support */
+#define VEX_HWCAPS_AMD64_CX16 (1<<5) /* cmpxchg16b support */
/* ppc32: baseline capability is integer only */
-#define VEX_HWCAPS_PPC32_F (1<<5) /* basic (non-optional) FP */
-#define VEX_HWCAPS_PPC32_V (1<<6) /* Altivec (VMX) */
-#define VEX_HWCAPS_PPC32_FX (1<<7) /* FP extns (fsqrt, fsqrts) */
-#define VEX_HWCAPS_PPC32_GX (1<<8) /* Graphics extns
+#define VEX_HWCAPS_PPC32_F (1<<6) /* basic (non-optional) FP */
+#define VEX_HWCAPS_PPC32_V (1<<7) /* Altivec (VMX) */
+#define VEX_HWCAPS_PPC32_FX (1<<8) /* FP extns (fsqrt, fsqrts) */
+#define VEX_HWCAPS_PPC32_GX (1<<9) /* Graphics extns
(fres,frsqrte,fsel,stfiwx) */
/* ppc64: baseline capability is integer and basic FP insns */
-#define VEX_HWCAPS_PPC64_V (1<<9) /* Altivec (VMX) */
-#define VEX_HWCAPS_PPC64_FX (1<<10) /* FP extns (fsqrt, fsqrts) */
-#define VEX_HWCAPS_PPC64_GX (1<<11) /* Graphics extns
+#define VEX_HWCAPS_PPC64_V (1<<10) /* Altivec (VMX) */
+#define VEX_HWCAPS_PPC64_FX (1<<11) /* FP extns (fsqrt, fsqrts) */
+#define VEX_HWCAPS_PPC64_GX (1<<12) /* Graphics extns
(fres,frsqrte,fsel,stfiwx) */
/* arm: baseline capability is ARMv4 */
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