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From: Dominic A. <zer...@go...> - 2009-04-19 10:59:20
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Hi Josef,
Yes, thank you. The second call to the cache model is indeed not
necessary as it will
always hit. Thus the performance loss should be even lower.
My extended cache-model will still need to be called though - but that
is a different story.
Performance will probably stay about the same unless your compiler/architecture
moves to a vastly different operating point ;-) Something I have
noticed recently
with different gcc-options!
-Dominic
On Sun, Apr 19, 2009 at 12:55 AM, Josef Weidendorfer
<Jos...@gm...> wrote:
> On Saturday 18 April 2009, Dominic Account wrote:
>> I hope I did not introduce new bugs here. Please, review
>> my patch.
>
> Just a minor remark: inlining the patch would have made it easier.
>
>> +void log_1I_1Dm_cache_access(InstrInfo* n, Addr data_addr, Word data_size)
>> +{
>> + //VG_(printf)("1I_1Dm: CCaddr=0x%010lx, iaddr=0x%010lx, isize=%lu\n"
>> + // " daddr=0x%010lx, dsize=%lu\n",
>> + // n, n->instr_addr, n->instr_len, data_addr, data_size);
>> + cachesim_I1_doref(n->instr_addr, n->instr_len,
>> + &n->parent->Ir.m1, &n->parent->Ir.m2);
>> + n->parent->Ir.a++;
>> +
>> + cachesim_D1_doref(data_addr, data_size,
>> + &n->parent->Dr.m1, &n->parent->Dr.m2);
>> + cachesim_D1_doref(data_addr, data_size,
>> + &n->parent->Dw.m1, &n->parent->Dw.m2);
>
> Given the cache model and the fact that no other thread can access the cache
> inbetween, the second call into the simulator should not be needed, as it always
> will be a L1 hit. Same for other handlers.
> It would be interesting to see the performance hit introduced by your patch.
>
> Josef
>
>> +
>> + n->parent->Dr.a++;
>> + n->parent->Dw.a++;
>> +}
>
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