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[Valgrind-developers] valgrind: r9315 - branches/DARWIN/none/tests/x86
|
From: <sv...@va...> - 2009-03-04 04:12:01
|
Author: njn
Date: 2009-03-04 04:11:52 +0000 (Wed, 04 Mar 2009)
New Revision: 9315
Log:
Avoid using %ebx in the insn_* tests, because it's the PIC register and
must not be clobbered (PIC is apparently on by default on Darwin). They all
now give the right stdout output, and the stderr output is wrong only
because of a warning about sigaction() being unimplemented.
Modified:
branches/DARWIN/none/tests/x86/Makefile.am
branches/DARWIN/none/tests/x86/gen_insn_test.pl
branches/DARWIN/none/tests/x86/insn_basic.def
Modified: branches/DARWIN/none/tests/x86/Makefile.am
===================================================================
--- branches/DARWIN/none/tests/x86/Makefile.am 2009-03-04 01:23:04 UTC (rev 9314)
+++ branches/DARWIN/none/tests/x86/Makefile.am 2009-03-04 04:11:52 UTC (rev 9315)
@@ -65,6 +65,7 @@
cse_fail \
fpu_lazy_eflags \
getseg \
+ $(INSN_TESTS) \
movx int pushpopseg \
smc1 yield
if BUILD_SSSE3_TESTS
@@ -84,7 +85,6 @@
fcmovnu \
fxtract \
incdec_alt \
- $(INSN_TESTS) \
jcxz \
lahf \
looper \
Modified: branches/DARWIN/none/tests/x86/gen_insn_test.pl
===================================================================
--- branches/DARWIN/none/tests/x86/gen_insn_test.pl 2009-03-04 01:23:04 UTC (rev 9314)
+++ branches/DARWIN/none/tests/x86/gen_insn_test.pl 2009-03-04 04:11:52 UTC (rev 9315)
@@ -48,34 +48,36 @@
);
our %RegNums = (
+ # We avoid using %ebx and %bx because %ebx is the PIC
+ # register on Darwin and so cannot be clobbered.
al => 0, ax => 0, eax => 0,
- bl => 1, bx => 1, ebx => 1,
- cl => 2, cx => 2, ecx => 2,
- dl => 3, dx => 3, edx => 3,
+ cl => 1, cx => 1, ecx => 1,
+ dl => 2, dx => 2, edx => 2,
+ bl => 3, si => 3, esi => 3,
ah => 4,
- bh => 5,
- ch => 6,
- dh => 7,
+ ch => 5,
+ dh => 6,
+ bh => 7,
st0 => 0, st1 => 1, st2 => 2, st3 => 3,
st4 => 4, st5 => 5, st6 => 6, st7 => 7
);
our %RegTypes = (
al => "r8", ah => "r8", ax => "r16", eax => "r32",
- bl => "r8", bh => "r8", bx => "r16", ebx => "r32",
cl => "r8", ch => "r8", cx => "r16", ecx => "r32",
- dl => "r8", dh => "r8", dx => "r16", edx => "r32"
+ dl => "r8", dh => "r8", dx => "r16", edx => "r32",
+ bl => "r8", bh => "r8", si => "r16", esi => "r32"
);
our @IntRegs = (
{ r8 => "al", r16 => "ax", r32 => "eax" },
- { r8 => "bl", r16 => "bx", r32 => "ebx" },
{ r8 => "cl", r16 => "cx", r32 => "ecx" },
{ r8 => "dl", r16 => "dx", r32 => "edx" },
+ { r8 => "bl", r16 => "si", r32 => "esi" },
{ r8 => "ah" },
- { r8 => "bh" },
{ r8 => "ch" },
- { r8 => "dh" }
+ { r8 => "dh" },
+ { r8 => "bh" }
);
print <<EOF;
@@ -328,7 +330,7 @@
{
my $name = "arg$argc";
- if ($arg =~ /^([abcd]l|[abcd]x|e[abcd]x|r8|r16|r32|mm|xmm|m8|m16|m32|m64|m128)\.(sb|ub|sw|uw|sd|ud|sq|uq|ps|pd)\[([^\]]+)\]$/)
+ if ($arg =~ /^([abcd]l|[abcd]x|e[abcd]x|si|esi|r8|r16|r32|mm|xmm|m8|m16|m32|m64|m128)\.(sb|ub|sw|uw|sd|ud|sq|uq|ps|pd)\[([^\]]+)\]$/)
{
my $type = $RegTypes{$1} || $1;
my $regnum = $RegNums{$1};
Modified: branches/DARWIN/none/tests/x86/insn_basic.def
===================================================================
--- branches/DARWIN/none/tests/x86/insn_basic.def 2009-03-04 01:23:04 UTC (rev 9314)
+++ branches/DARWIN/none/tests/x86/insn_basic.def 2009-03-04 04:11:52 UTC (rev 9315)
@@ -20,8 +20,8 @@
###aas eflags[0x11,0x10] al.ub[0xf] ah.ub[0x2] : => al.ub[0x9] ah.ub[0x01] eflags[0x11,0x11]
adcb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[46]
adcb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[47]
-adcb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[46]
-adcb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[47]
+adcb eflags[0x1,0x0] : imm8[12] cl.ub[34] => 1.ub[46]
+adcb eflags[0x1,0x1] : imm8[12] cl.ub[34] => 1.ub[47]
adcb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[46]
adcb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[47]
adcb eflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[46]
@@ -34,8 +34,8 @@
adcw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3469]
adcw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912]
adcw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913]
-adcw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[6912]
-adcw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[6913]
+adcw eflags[0x1,0x0] : imm16[1234] si.uw[5678] => 1.uw[6912]
+adcw eflags[0x1,0x1] : imm16[1234] si.uw[5678] => 1.uw[6913]
adcw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[6912]
adcw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[6913]
adcw eflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[6912]
@@ -48,8 +48,8 @@
adcl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334]
adcl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[99999999]
adcl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[100000000]
-adcl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[99999999]
-adcl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[100000000]
+adcl eflags[0x1,0x0] : imm32[12345678] esi.ud[87654321] => 1.ud[99999999]
+adcl eflags[0x1,0x1] : imm32[12345678] esi.ud[87654321] => 1.ud[100000000]
adcl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[99999999]
adcl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[100000000]
adcl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
@@ -59,41 +59,41 @@
adcl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
adcl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
addb imm8[12] al.ub[34] => 1.ub[46]
-addb imm8[12] bl.ub[34] => 1.ub[46]
+addb imm8[12] cl.ub[34] => 1.ub[46]
addb imm8[12] m8.ub[34] => 1.ub[46]
addb r8.ub[12] r8.ub[34] => 1.ub[46]
addb r8.ub[12] m8.ub[34] => 1.ub[46]
addb m8.ub[12] r8.ub[34] => 1.ub[46]
addw imm8[12] r16.uw[3456] => 1.uw[3468]
addw imm16[1234] ax.uw[5678] => 1.uw[6912]
-addw imm16[1234] bx.uw[5678] => 1.uw[6912]
+addw imm16[1234] si.uw[5678] => 1.uw[6912]
addw imm16[1234] m16.uw[5678] => 1.uw[6912]
addw r16.uw[1234] r16.uw[5678] => 1.uw[6912]
addw r16.uw[1234] m16.uw[5678] => 1.uw[6912]
addw m16.uw[1234] r16.uw[5678] => 1.uw[6912]
addl imm8[12] r32.ud[87654321] => 1.ud[87654333]
addl imm32[12345678] eax.ud[87654321] => 1.ud[99999999]
-addl imm32[12345678] ebx.ud[87654321] => 1.ud[99999999]
+addl imm32[12345678] esi.ud[87654321] => 1.ud[99999999]
addl imm32[12345678] m32.ud[87654321] => 1.ud[99999999]
addl r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
addl r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999]
addl m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
andb imm8[0x34] al.ub[0x56] => 1.ub[0x14]
-andb imm8[0x34] bl.ub[0x56] => 1.ub[0x14]
+andb imm8[0x34] cl.ub[0x56] => 1.ub[0x14]
andb imm8[0x34] m8.ub[0x56] => 1.ub[0x14]
andb r8.ub[0x34] r8.ub[0x56] => 1.ub[0x14]
andb r8.ub[0x34] m8.ub[0x56] => 1.ub[0x14]
andb m8.ub[0x34] r8.ub[0x56] => 1.ub[0x14]
andw imm8[0x31] r16.uw[0x1234] => 1.uw[0x0030]
andw imm16[0x4231] ax.uw[0x1234] => 1.uw[0x0230]
-andw imm16[0x4231] bx.uw[0x1234] => 1.uw[0x0230]
+andw imm16[0x4231] si.uw[0x1234] => 1.uw[0x0230]
andw imm16[0x4231] m16.uw[0x1234] => 1.uw[0x0230]
andw r16.uw[0x4231] r16.uw[0x1234] => 1.uw[0x0230]
andw r16.uw[0x4231] m16.uw[0x1234] => 1.uw[0x0230]
andw m16.uw[0x4231] r16.uw[0x1234] => 1.uw[0x0230]
andl imm8[0x31] r32.ud[0x12345678] => 1.ud[0x00000030]
andl imm32[0x86427531] eax.ud[0x12345678] => 1.ud[0x02005430]
-andl imm32[0x86427531] ebx.ud[0x12345678] => 1.ud[0x02005430]
+andl imm32[0x86427531] esi.ud[0x12345678] => 1.ud[0x02005430]
andl imm32[0x86427531] m32.ud[0x12345678] => 1.ud[0x02005430]
andl r32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x02005430]
andl r32.ud[0x86427531] m32.ud[0x12345678] => 1.ud[0x02005430]
@@ -514,21 +514,21 @@
notl r32.ud[0xff00f0ca] => 0.ud[0x00ff0f35]
notl m32.ud[0xff00f0ca] => 0.ud[0x00ff0f35]
orb imm8[0x34] al.ub[0x56] => 1.ub[0x76]
-orb imm8[0x34] bl.ub[0x56] => 1.ub[0x76]
+orb imm8[0x34] cl.ub[0x56] => 1.ub[0x76]
orb imm8[0x34] m8.ub[0x56] => 1.ub[0x76]
orb r8.ub[0x34] r8.ub[0x56] => 1.ub[0x76]
orb r8.ub[0x34] m8.ub[0x56] => 1.ub[0x76]
orb m8.ub[0x34] r8.ub[0x56] => 1.ub[0x76]
orw imm8[0x31] r16.uw[0x1234] => 1.uw[0x1235]
orw imm16[0x4231] ax.uw[0x1234] => 1.uw[0x5235]
-orw imm16[0x4231] bx.uw[0x1234] => 1.uw[0x5235]
+orw imm16[0x4231] si.uw[0x1234] => 1.uw[0x5235]
orw imm16[0x4231] m16.uw[0x1234] => 1.uw[0x5235]
orw r16.uw[0x4231] r16.uw[0x1234] => 1.uw[0x5235]
orw r16.uw[0x4231] m16.uw[0x1234] => 1.uw[0x5235]
orw m16.uw[0x4231] r16.uw[0x1234] => 1.uw[0x5235]
orl imm8[0x31] r32.ud[0x12345678] => 1.ud[0x12345679]
orl imm32[0x86427531] eax.ud[0x12345678] => 1.ud[0x96767779]
-orl imm32[0x86427531] ebx.ud[0x12345678] => 1.ud[0x96767779]
+orl imm32[0x86427531] esi.ud[0x12345678] => 1.ud[0x96767779]
orl imm32[0x86427531] m32.ud[0x12345678] => 1.ud[0x96767779]
orl r32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x96767779]
orl r32.ud[0x86427531] m32.ud[0x12345678] => 1.ud[0x96767779]
@@ -645,8 +645,8 @@
sarl cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0xffff00f0]
sbbb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[22]
sbbb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[21]
-sbbb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[22]
-sbbb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[21]
+sbbb eflags[0x1,0x0] : imm8[12] cl.ub[34] => 1.ub[22]
+sbbb eflags[0x1,0x1] : imm8[12] cl.ub[34] => 1.ub[21]
sbbb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[22]
sbbb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[21]
sbbb eflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[22]
@@ -659,8 +659,8 @@
sbbw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3443]
sbbw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[4444]
sbbw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[4443]
-sbbw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[4444]
-sbbw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[4443]
+sbbw eflags[0x1,0x0] : imm16[1234] si.uw[5678] => 1.uw[4444]
+sbbw eflags[0x1,0x1] : imm16[1234] si.uw[5678] => 1.uw[4443]
sbbw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[4444]
sbbw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[4443]
sbbw eflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[4444]
@@ -673,8 +673,8 @@
sbbl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654308]
sbbl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[75308643]
sbbl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[75308642]
-sbbl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308643]
-sbbl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308642]
+sbbl eflags[0x1,0x0] : imm32[12345678] esi.ud[87654321] => 1.ud[75308643]
+sbbl eflags[0x1,0x1] : imm32[12345678] esi.ud[87654321] => 1.ud[75308642]
sbbl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[75308643]
sbbl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[75308642]
sbbl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
@@ -948,14 +948,14 @@
std eflags[0x400,0x000] : => eflags[0x400,0x400]
std eflags[0x400,0x400] : => eflags[0x400,0x400]
subb imm8[12] al.ub[34] => 1.ub[22]
-subb imm8[12] bl.ub[34] => 1.ub[22]
+subb imm8[12] cl.ub[34] => 1.ub[22]
subb imm8[12] m8.ub[34] => 1.ub[22]
subb r8.ub[12] r8.ub[34] => 1.ub[22]
subb r8.ub[12] m8.ub[34] => 1.ub[22]
subb m8.ub[12] r8.ub[34] => 1.ub[22]
subw imm8[12] r16.uw[3456] => 1.uw[3444]
subw imm16[1234] ax.uw[5678] => 1.uw[4444]
-subw imm16[1234] bx.uw[5678] => 1.uw[4444]
+subw imm16[1234] si.uw[5678] => 1.uw[4444]
subw imm16[1234] m16.uw[5678] => 1.uw[4444]
subw r16.uw[1234] r16.uw[5678] => 1.uw[4444]
subw r16.uw[1234] m16.uw[5678] => 1.uw[4444]
@@ -963,7 +963,7 @@
subl imm8[12] r32.ud[87654321] => 1.ud[87654309]
subl imm32[12345678] r32.ud[87654321] => 1.ud[75308643]
subl imm32[12345678] eax.ud[87654321] => 1.ud[75308643]
-subl imm32[12345678] ebx.ud[87654321] => 1.ud[75308643]
+subl imm32[12345678] esi.ud[87654321] => 1.ud[75308643]
subl r32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
subl r32.ud[12345678] m32.ud[87654321] => 1.ud[75308643]
subl m32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
@@ -972,11 +972,11 @@
testb imm8[0x1a] al.ub[0xa1] => eflags[0x8c5,0x044]
testb imm8[0xa1] al.ub[0xa1] => eflags[0x8c5,0x080]
testb imm8[0xa5] al.ub[0xa5] => eflags[0x8c5,0x084]
-testb imm8[0x1a] bl.ub[0x1a] => eflags[0x8c5,0x000]
-testb imm8[0x5a] bl.ub[0x5a] => eflags[0x8c5,0x004]
-testb imm8[0x1a] bl.ub[0xa1] => eflags[0x8c5,0x044]
-testb imm8[0xa1] bl.ub[0xa1] => eflags[0x8c5,0x080]
-testb imm8[0xa5] bl.ub[0xa5] => eflags[0x8c5,0x084]
+testb imm8[0x1a] cl.ub[0x1a] => eflags[0x8c5,0x000]
+testb imm8[0x5a] cl.ub[0x5a] => eflags[0x8c5,0x004]
+testb imm8[0x1a] cl.ub[0xa1] => eflags[0x8c5,0x044]
+testb imm8[0xa1] cl.ub[0xa1] => eflags[0x8c5,0x080]
+testb imm8[0xa5] cl.ub[0xa5] => eflags[0x8c5,0x084]
testb imm8[0x1a] m8.ub[0x1a] => eflags[0x8c5,0x000]
testb imm8[0x5a] m8.ub[0x5a] => eflags[0x8c5,0x004]
testb imm8[0x1a] m8.ub[0xa1] => eflags[0x8c5,0x044]
@@ -997,11 +997,11 @@
testw imm16[0x1a1a] ax.uw[0xa1a1] => eflags[0x8c5,0x044]
testw imm16[0xa1a1] ax.uw[0xa1a1] => eflags[0x8c5,0x080]
testw imm16[0xa5a5] ax.uw[0xa5a5] => eflags[0x8c5,0x084]
-testw imm16[0x1a1a] bx.uw[0x1a1a] => eflags[0x8c5,0x000]
-testw imm16[0x5a5a] bx.uw[0x5a5a] => eflags[0x8c5,0x004]
-testw imm16[0x1a1a] bx.uw[0xa1a1] => eflags[0x8c5,0x044]
-testw imm16[0xa1a1] bx.uw[0xa1a1] => eflags[0x8c5,0x080]
-testw imm16[0xa5a5] bx.uw[0xa5a5] => eflags[0x8c5,0x084]
+testw imm16[0x1a1a] si.uw[0x1a1a] => eflags[0x8c5,0x000]
+testw imm16[0x5a5a] si.uw[0x5a5a] => eflags[0x8c5,0x004]
+testw imm16[0x1a1a] si.uw[0xa1a1] => eflags[0x8c5,0x044]
+testw imm16[0xa1a1] si.uw[0xa1a1] => eflags[0x8c5,0x080]
+testw imm16[0xa5a5] si.uw[0xa5a5] => eflags[0x8c5,0x084]
testw imm16[0x1a1a] m16.uw[0x1a1a] => eflags[0x8c5,0x000]
testw imm16[0x5a5a] m16.uw[0x5a5a] => eflags[0x8c5,0x004]
testw imm16[0x1a1a] m16.uw[0xa1a1] => eflags[0x8c5,0x044]
@@ -1022,11 +1022,11 @@
testl imm32[0x1a1a1a1a] eax.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
testl imm32[0xa1a1a1a1] eax.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
testl imm32[0xa5a5a5a5] eax.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
-testl imm32[0x1a1a1a1a] ebx.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
-testl imm32[0x5a5a5a5a] ebx.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
-testl imm32[0x1a1a1a1a] ebx.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
-testl imm32[0xa1a1a1a1] ebx.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
-testl imm32[0xa5a5a5a5] ebx.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
+testl imm32[0x1a1a1a1a] esi.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
+testl imm32[0x5a5a5a5a] esi.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
+testl imm32[0x1a1a1a1a] esi.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
+testl imm32[0xa1a1a1a1] esi.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
+testl imm32[0xa5a5a5a5] esi.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
testl imm32[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
testl imm32[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
testl imm32[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
@@ -1051,32 +1051,32 @@
xchgb r8.ub[12] r8.ub[34] => 0.ub[34] 1.ub[12]
xchgb r8.ub[12] m8.ub[34] => 0.ub[34] 1.ub[12]
xchgb m8.ub[12] r8.ub[34] => 0.ub[34] 1.ub[12]
-xchgw ax.uw[1234] bx.uw[5678] => 0.uw[5678] 1.uw[1234]
-xchgw bx.uw[1234] ax.uw[5678] => 0.uw[5678] 1.uw[1234]
+xchgw ax.uw[1234] si.uw[5678] => 0.uw[5678] 1.uw[1234]
+xchgw si.uw[1234] ax.uw[5678] => 0.uw[5678] 1.uw[1234]
xchgw ax.uw[1234] cx.uw[5678] => 0.uw[5678] 1.uw[1234]
xchgw r16.uw[1234] m16.uw[5678] => 0.uw[5678] 1.uw[1234]
xchgw m16.uw[1234] r16.uw[5678] => 0.uw[5678] 1.uw[1234]
-xchgl eax.ud[12345678] ebx.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
-xchgl ebx.ud[12345678] eax.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
-xchgl ebx.ud[12345678] ecx.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
+xchgl eax.ud[12345678] esi.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
+xchgl esi.ud[12345678] eax.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
+xchgl esi.ud[12345678] ecx.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
xchgl r32.ud[12345678] m32.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
xchgl m32.ud[12345678] r32.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
xorb imm8[0x34] al.ub[0x56] => 1.ub[0x62]
-xorb imm8[0x34] bl.ub[0x56] => 1.ub[0x62]
+xorb imm8[0x34] cl.ub[0x56] => 1.ub[0x62]
xorb imm8[0x34] m8.ub[0x56] => 1.ub[0x62]
xorb r8.ub[0x34] r8.ub[0x56] => 1.ub[0x62]
xorb r8.ub[0x34] m8.ub[0x56] => 1.ub[0x62]
xorb m8.ub[0x34] r8.ub[0x56] => 1.ub[0x62]
xorw imm8[0x31] r16.uw[0x1234] => 1.uw[0x1205]
xorw imm16[0x4231] ax.uw[0x1234] => 1.uw[0x5005]
-xorw imm16[0x4231] bx.uw[0x1234] => 1.uw[0x5005]
+xorw imm16[0x4231] si.uw[0x1234] => 1.uw[0x5005]
xorw imm16[0x4231] m16.uw[0x1234] => 1.uw[0x5005]
xorw r16.uw[0x4231] r16.uw[0x1234] => 1.uw[0x5005]
xorw r16.uw[0x4231] m16.uw[0x1234] => 1.uw[0x5005]
xorw m16.uw[0x4231] r16.uw[0x1234] => 1.uw[0x5005]
xorl imm8[0x31] r32.ud[0x12345678] => 1.ud[0x12345649]
xorl imm32[0x86427531] eax.ud[0x12345678] => 1.ud[0x94762349]
-xorl imm32[0x86427531] ebx.ud[0x12345678] => 1.ud[0x94762349]
+xorl imm32[0x86427531] esi.ud[0x12345678] => 1.ud[0x94762349]
xorl imm32[0x86427531] m32.ud[0x12345678] => 1.ud[0x94762349]
xorl r32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x94762349]
xorl r32.ud[0x86427531] m32.ud[0x12345678] => 1.ud[0x94762349]
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