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From: Bart V. A. <bar...@gm...> - 2008-06-26 07:46:35
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On Wed, May 28, 2008 at 1:22 AM, Julian Seward <js...@ac...> wrote:
>
> Well, the difficulty is that the powerpc way of doing atomic
> test-and-set (etc) is completely different from the x86/amd64
> way. x86 and amd64 make it easy, by allowing a 1-byte LOCK prefix
> byte (0xF0) in front of the instruction. Vex sees that and puts
> Imbe_BusLock and Imbe_BusUnlock around the translation of the
> instruction, so helgrind and drd (and anybody else who cares) can
> see the locking.
Hello Julian,
What is your opinion about the patch below ? This patch allows
Helgrind and DRD to recognize stwcx instructions as atomic: if stwcx
performs a store, bus lock and bus unlock events are passed to
Valgrind tools around the actual store.
Index: priv/guest-ppc/toIR.c
===================================================================
--- priv/guest-ppc/toIR.c (revision 1856)
+++ priv/guest-ppc/toIR.c (working copy)
@@ -4896,7 +4896,9 @@
whether rS is stored is dependent on that value. */
/* Success? Do the (32bit) store */
+ stmt( IRStmt_MBE(Imbe_BusLock) );
storeBE( mkexpr(EA), mkSzNarrow32(ty, mkexpr(rS)) );
+ stmt( IRStmt_MBE(Imbe_BusUnlock) );
// Set CR0[LT GT EQ S0] = 0b001 || XER[SO]
putCR321(0, mkU8(1<<1));
Bart.
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