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From: <sv...@va...> - 2008-05-13 11:44:08
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Author: sewardj
Date: 2008-05-13 11:47:29 +0100 (Tue, 13 May 2008)
New Revision: 1847
Log:
Merge r1816,1817,1833: specialise NZ after SUBW(16) and NS after
SUBB(8), on both x86 and amd64.
Modified:
branches/VEX_3_3_BRANCH/priv/guest-amd64/ghelpers.c
branches/VEX_3_3_BRANCH/priv/guest-x86/ghelpers.c
Modified: branches/VEX_3_3_BRANCH/priv/guest-amd64/ghelpers.c
===================================================================
--- branches/VEX_3_3_BRANCH/priv/guest-amd64/ghelpers.c 2008-05-13 09:36:07 UTC (rev 1846)
+++ branches/VEX_3_3_BRANCH/priv/guest-amd64/ghelpers.c 2008-05-13 10:47:29 UTC (rev 1847)
@@ -1001,6 +1001,13 @@
unop(Iop_64to16,cc_dep1),
unop(Iop_64to16,cc_dep2)));
}
+ if (isU64(cc_op, AMD64G_CC_OP_SUBW) && isU64(cond, AMD64CondNZ)) {
+ /* word sub/cmp, then NZ --> test dst!=src */
+ return unop(Iop_1Uto64,
+ binop(Iop_CmpNE16,
+ unop(Iop_64to16,cc_dep1),
+ unop(Iop_64to16,cc_dep2)));
+ }
if (isU64(cc_op, AMD64G_CC_OP_SUBW) && isU64(cond, AMD64CondLE)) {
/* word sub/cmp, then LE (signed less than or equal)
@@ -1043,6 +1050,18 @@
binop(Iop_Shr64,cc_dep1,mkU8(7)),
mkU64(1));
}
+ if (isU64(cc_op, AMD64G_CC_OP_SUBB) && isU64(cond, AMD64CondNS)
+ && isU64(cc_dep2, 0)) {
+ /* byte sub/cmp of zero, then NS --> test !(dst-0 <s 0)
+ --> test !(dst <s 0)
+ --> (ULong) !dst[7]
+ */
+ return binop(Iop_Xor64,
+ binop(Iop_And64,
+ binop(Iop_Shr64,cc_dep1,mkU8(7)),
+ mkU64(1)),
+ mkU64(1));
+ }
/*---------------- LOGICQ ----------------*/
Modified: branches/VEX_3_3_BRANCH/priv/guest-x86/ghelpers.c
===================================================================
--- branches/VEX_3_3_BRANCH/priv/guest-x86/ghelpers.c 2008-05-13 09:36:07 UTC (rev 1846)
+++ branches/VEX_3_3_BRANCH/priv/guest-x86/ghelpers.c 2008-05-13 10:47:29 UTC (rev 1847)
@@ -925,6 +925,13 @@
unop(Iop_32to16,cc_dep1),
unop(Iop_32to16,cc_dep2)));
}
+ if (isU32(cc_op, X86G_CC_OP_SUBW) && isU32(cond, X86CondNZ)) {
+ /* word sub/cmp, then NZ --> test dst!=src */
+ return unop(Iop_1Uto32,
+ binop(Iop_CmpNE16,
+ unop(Iop_32to16,cc_dep1),
+ unop(Iop_32to16,cc_dep2)));
+ }
/*---------------- SUBB ----------------*/
@@ -967,6 +974,18 @@
binop(Iop_Shr32,cc_dep1,mkU8(7)),
mkU32(1));
}
+ if (isU32(cc_op, X86G_CC_OP_SUBB) && isU32(cond, X86CondNS)
+ && isU32(cc_dep2, 0)) {
+ /* byte sub/cmp of zero, then NS --> test !(dst-0 <s 0)
+ --> test !(dst <s 0)
+ --> (UInt) !dst[7]
+ */
+ return binop(Iop_Xor32,
+ binop(Iop_And32,
+ binop(Iop_Shr32,cc_dep1,mkU8(7)),
+ mkU32(1)),
+ mkU32(1));
+ }
/*---------------- LOGICL ----------------*/
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