|
From: <sv...@va...> - 2008-05-12 23:09:05
|
Author: sewardj
Date: 2008-05-13 00:09:09 +0100 (Tue, 13 May 2008)
New Revision: 1839
Log:
Handle Left64 on 32-bit host. This stops Memcheck on ppc32 asserting
on some bits of Altivec code. Partial merge of r1832.
Modified:
branches/VEX_3_3_BRANCH/priv/host-ppc/isel.c
Modified: branches/VEX_3_3_BRANCH/priv/host-ppc/isel.c
===================================================================
--- branches/VEX_3_3_BRANCH/priv/host-ppc/isel.c 2008-05-11 10:11:58 UTC (rev 1838)
+++ branches/VEX_3_3_BRANCH/priv/host-ppc/isel.c 2008-05-12 23:09:09 UTC (rev 1839)
@@ -2751,6 +2751,28 @@
return;
}
+ /* Left64 */
+ case Iop_Left64: {
+ HReg argHi, argLo;
+ HReg zero32 = newVRegI(env);
+ HReg resHi = newVRegI(env);
+ HReg resLo = newVRegI(env);
+ iselInt64Expr(&argHi, &argLo, env, e->Iex.Unop.arg);
+ vassert(env->mode64 == False);
+ addInstr(env, PPCInstr_LI(zero32, 0, env->mode64));
+ /* resHi:resLo = - argHi:argLo */
+ addInstr(env, PPCInstr_AddSubC( False/*sub*/, True/*set carry*/,
+ resLo, zero32, argLo ));
+ addInstr(env, PPCInstr_AddSubC( False/*sub*/, False/*read carry*/,
+ resHi, zero32, argHi ));
+ /* resHi:resLo |= srcHi:srcLo */
+ addInstr(env, PPCInstr_Alu(Palu_OR, resLo, resLo, PPCRH_Reg(argLo)));
+ addInstr(env, PPCInstr_Alu(Palu_OR, resHi, resHi, PPCRH_Reg(argHi)));
+ *rHi = resHi;
+ *rLo = resLo;
+ return;
+ }
+
/* 32Sto64(e) */
case Iop_32Sto64: {
HReg tHi = newVRegI(env);
|