[Valgrind-developers] valgrind: r7968 - in branches/OTRACK_BY_INSTRUMENTATION/coregrind: . m_scheduler

[<sv...@va...>]

Author: sewardj
Date: 2008-05-01 11:08:39 +0100 (Thu, 01 May 2008)
New Revision: 7968

Log:

Try to navigate out of the confusing maze of requirements on vex guest
state sizes and alignments, by simply insisting on 16-byte size and
alignment for everything.

In summary, all 4 areas (guest state, first shadow area, second shadow
area, spill area) must have 16-aligned sizes and 16-aligned addresses,
and be placed back-to-back (no holes in between).



Modified:
   branches/OTRACK_BY_INSTRUMENTATION/coregrind/m_scheduler/scheduler.c
   branches/OTRACK_BY_INSTRUMENTATION/coregrind/pub_core_threadstate.h


Modified: branches/OTRACK_BY_INSTRUMENTATION/coregrind/m_scheduler/scheduler.c
===================================================================
--- branches/OTRACK_BY_INSTRUMENTATION/coregrind/m_scheduler/scheduler.c	2008-05-01 09:19:51 UTC (rev 7967)
+++ branches/OTRACK_BY_INSTRUMENTATION/coregrind/m_scheduler/scheduler.c	2008-05-01 10:08:39 UTC (rev 7968)
@@ -531,7 +531,11 @@
 
 /* Do various guest state alignment checks prior to running a thread.
    Specifically, check that what we have matches Vex's guest state
-   layout requirements. */
+   layout requirements.  See libvex.h for details, but in short the
+   requirements are: There must be no holes in between the primary
+   guest state, its two copies, and the spill area.  In short, all 4
+   areas must have a 16-aligned size and be 16-aligned, and placed
+   back-to-back. */
 static void do_pre_run_checks ( ThreadState* tst )
 {
    Addr a_vex     = (Addr) & tst->arch.vex;
@@ -544,19 +548,22 @@
    UInt sz_spill  = (UInt) sizeof tst->arch.vex_spill;
 
    if (0)
-   VG_(printf)("%p %d %p %d %p %d\n",
-               (void*)a_vex, sz_vex, (void*)a_vexsh1, sz_vexsh1,
+   VG_(printf)("gst %p %d, sh1 %p %d, "
+               "sh2 %p %d, spill %p %d\n",
+               (void*)a_vex, sz_vex,
+               (void*)a_vexsh1, sz_vexsh1,
+               (void*)a_vexsh2, sz_vexsh2,
                (void*)a_spill, sz_spill );
 
-   vg_assert(VG_IS_8_ALIGNED(sz_vex));
-   vg_assert(VG_IS_8_ALIGNED(sz_vexsh1));
-   vg_assert(VG_IS_8_ALIGNED(sz_vexsh2));
+   vg_assert(VG_IS_16_ALIGNED(sz_vex));
+   vg_assert(VG_IS_16_ALIGNED(sz_vexsh1));
+   vg_assert(VG_IS_16_ALIGNED(sz_vexsh2));
    vg_assert(VG_IS_16_ALIGNED(sz_spill));
 
-   vg_assert(VG_IS_4_ALIGNED(a_vex));
-   vg_assert(VG_IS_4_ALIGNED(a_vexsh1));
-   vg_assert(VG_IS_4_ALIGNED(a_vexsh2));
-   vg_assert(VG_IS_4_ALIGNED(a_spill));
+   vg_assert(VG_IS_16_ALIGNED(a_vex));
+   vg_assert(VG_IS_16_ALIGNED(a_vexsh1));
+   vg_assert(VG_IS_16_ALIGNED(a_vexsh2));
+   vg_assert(VG_IS_16_ALIGNED(a_spill));
 
    /* Check that the guest state and its two shadows have the same
       size, and that there are no holes in between.  The latter is
@@ -582,8 +589,6 @@
    vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex.guest_VR1));
    vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow1.guest_VR1));
    vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow2.guest_VR1));
-   /* and the spill area must also be 16-aligned */
-   vg_assert(VG_IS_16_ALIGNED(a_spill));
 #  endif   
 }
 

Modified: branches/OTRACK_BY_INSTRUMENTATION/coregrind/pub_core_threadstate.h
===================================================================
--- branches/OTRACK_BY_INSTRUMENTATION/coregrind/pub_core_threadstate.h	2008-05-01 09:19:51 UTC (rev 7967)
+++ branches/OTRACK_BY_INSTRUMENTATION/coregrind/pub_core_threadstate.h	2008-05-01 10:08:39 UTC (rev 7968)
@@ -93,15 +93,21 @@
    struct {
       /* --- BEGIN vex-mandated guest state --- */
 
+      /* Note that for code generation reasons, we require that the
+         guest state area, its two shadows, and the spill area, are
+         16-aligned and have 16-aligned sizes, and there are no holes
+         in between.  This is checked by do_pre_run_checks() in
+         scheduler.c. */
+
       /* Saved machine context. */
-      VexGuestArchState __attribute__((aligned(16))) vex;
+      VexGuestArchState vex __attribute__((aligned(16)));
 
       /* Saved shadow context (2 copies). */
-      VexGuestArchState __attribute__((aligned(16))) vex_shadow1;
-      VexGuestArchState __attribute__((aligned(16))) vex_shadow2;
+      VexGuestArchState vex_shadow1 __attribute__((aligned(16)));
+      VexGuestArchState vex_shadow2 __attribute__((aligned(16)));
 
       /* Spill area. */
-      UChar vex_spill[LibVEX_N_SPILL_BYTES];
+      UChar vex_spill[LibVEX_N_SPILL_BYTES] __attribute__((aligned(16)));
 
       /* --- END vex-mandated guest state --- */
    }