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From: Joyeau S. (Quartz) <Syl...@th...> - 2008-03-27 13:55:18
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Hi all,
Without being familiar with VEX, I propose a correction to Aron's patch
supporting isel instruction on e500 core.
Thereafter is the patch to apply on official v3.3.0:
--- valgrind-3.3.0/VEX/priv/guest-ppc/toIR.c 2007-12-11
00:18:52.000000000 +0100
+++ valgrind-3.3.0-isel/VEX/priv/guest-ppc/toIR.c 2008-03-27
12:37:26.372216000 +0100
@@ -8823,7 +8823,38 @@
-
+static Bool dis_int_isel ( UInt theInstr )
+{
+ UChar rD_addr = ifieldRegDS(theInstr);
+ UChar rA_addr = ifieldRegA(theInstr);
+ UChar rB_addr = ifieldRegB(theInstr);
+ UChar cr_bit = ifieldRegC(theInstr);
+
+ IRType ty = mode64 ? Ity_I64 : Ity_I32;
+ IRTemp rD = newTemp(ty);
+ IRTemp rA = newTemp(ty);
+ IRTemp rB = newTemp(ty);
+ IRTemp cr = newTemp(ty);
+ IRTemp cc_bitset = newTemp(ty);
+
+ DIP("isel. r%u,r%u,r%u,crb%u\n", rD_addr, rA_addr, rB_addr, cr_bit);
+
+ assign( rA, ea_rAor0(rA_addr) );
+ assign( rB, getIReg(rB_addr) );
+ assign( cr, getCRbit(cr_bit) );
+
+ assign( cc_bitset, binop(Iop_And32, mkexpr(cr), mkU32(1)));
+
+ assign( rD, IRExpr_Mux0X(
+ unop(Iop_1Uto8,
+ binop(Iop_CmpEQ32,
+ mkexpr(cc_bitset),
+ mkU32(0))),
+ mkexpr(rA),
+ mkexpr(rB)));
+ putIReg( rD_addr, mkexpr(rD) );
+ return True;
+}
/*------------------------------------------------------------*/
/*--- Disassemble a single instruction ---*/
@@ -9194,6 +9225,11 @@
case 0x1F:
+
+ if(IFIELD(theInstr,0,5)==0x1e) {
+ if (dis_int_isel( theInstr )) goto decode_success;
+ goto decode_failure;
+ }
/* For arith instns, bit10 is the OE flag (overflow enable) */
Hope this help,
BR
--
sj
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