|
From: Nuno L. <nun...@sa...> - 2008-03-26 13:23:35
|
>>> 20 movl 0x2A8(%ebp),%edx ; load %vr30 from memory >>> 21 andl $0xFFFF,%edx >>> 22 movl 0x2A8(%ebp),%edx ; <-- %vr30 is in %edx, not in memory >>> 23 movl %edi,%eax >>> 24 call[2] 0x38006C30 >>> >>> So the problem is that the register allocator gets confused somehow and >>> loads %vr30 twice, destroying its value (i.e. the line 22 is bogus and >>> could be removed altogether). >> >> That's very strange. After the reload on line 20, it should indeed >> have noted that %vr30 is now in %edx, so then there would be no need >> to incorrectly reload it again at line 22. I have no idea why. > > So well, any idea on how to debug that problem? I have zero knowledge > about > register allocation algorithms, hence my relutance to get my hands on it.. So this patch almost fixes the problem: http://web.ist.utl.pt/nuno.lopes/vex_regalloc_mov_vr.txt It removes mov instructions between a virtual register and a real register, as long as the virtual register is mapped to the real register. But then it fails the sanity check at line 939 (rreg_state[k].disp == Unavail) for the rreg of the previous mov instruction we had just skip. So, the idea seems ok, but the patch needs some work to fix that assertion. Julian, could you take a look at it, please? Thanks, Nuno ------------------- output of regalloc showing the bug: ====----====---- Insn 15 ----====----==== ---- movl %vr30,%edx Initial state: rreg_state[ 0] = %eax Free rreg_state[ 1] = %ebx BoundTo %vr8 rreg_state[ 2] = %ecx Free rreg_state[ 3] = %edx BoundTo %vr30 rreg_state[ 4] = %esi BoundTo %vr68 rreg_state[ 5] = %edi BoundTo %vr1 rreg_state[ 6] = %fake0 Free rreg_state[ 7] = %fake1 Free rreg_state[ 8] = %fake2 Free rreg_state[ 9] = %fake3 Free rreg_state[10] = %fake4 Free rreg_state[11] = %fake5 Free rreg_state[12] = %xmm0 Free rreg_state[13] = %xmm1 Free rreg_state[14] = %xmm2 Free rreg_state[15] = %xmm3 Free rreg_state[16] = %xmm4 Free rreg_state[17] = %xmm5 Free rreg_state[18] = %xmm6 Free rreg_state[19] = %xmm7 Free vreg_state[0 .. 77]: [1] -> 5 [8] -> 1 [30] -> 3 [68] -> 4 need to free up rreg: %edx After pre-insn actions for fixed regs: rreg_state[ 0] = %eax Free rreg_state[ 1] = %ebx BoundTo %vr8 rreg_state[ 2] = %ecx Free rreg_state[ 3] = %edx Unavail rreg_state[ 4] = %esi BoundTo %vr68 rreg_state[ 5] = %edi BoundTo %vr1 rreg_state[ 6] = %fake0 Free rreg_state[ 7] = %fake1 Free rreg_state[ 8] = %fake2 Free rreg_state[ 9] = %fake3 Free rreg_state[10] = %fake4 Free rreg_state[11] = %fake5 Free rreg_state[12] = %xmm0 Free rreg_state[13] = %xmm1 Free rreg_state[14] = %xmm2 Free rreg_state[15] = %xmm3 Free rreg_state[16] = %xmm4 Free rreg_state[17] = %xmm5 Free rreg_state[18] = %xmm6 Free rreg_state[19] = %xmm7 Free vreg_state[0 .. 77]: [1] -> 5 [8] -> 1 [68] -> 4 ** movl 0x2A8(%ebp),%edx After dealing with current insn: rreg_state[ 0] = %eax Free rreg_state[ 1] = %ebx BoundTo %vr8 rreg_state[ 2] = %ecx Free rreg_state[ 3] = %edx Unavail rreg_state[ 4] = %esi BoundTo %vr68 rreg_state[ 5] = %edi BoundTo %vr1 rreg_state[ 6] = %fake0 Free rreg_state[ 7] = %fake1 Free rreg_state[ 8] = %fake2 Free rreg_state[ 9] = %fake3 Free rreg_state[10] = %fake4 Free rreg_state[11] = %fake5 Free rreg_state[12] = %xmm0 Free rreg_state[13] = %xmm1 Free rreg_state[14] = %xmm2 Free rreg_state[15] = %xmm3 Free rreg_state[16] = %xmm4 Free rreg_state[17] = %xmm5 Free rreg_state[18] = %xmm6 Free rreg_state[19] = %xmm7 Free vreg_state[0 .. 77]: [1] -> 5 [8] -> 1 [68] -> 4 After post-insn actions for fixed regs: rreg_state[ 0] = %eax Free rreg_state[ 1] = %ebx BoundTo %vr8 rreg_state[ 2] = %ecx Free rreg_state[ 3] = %edx Unavail rreg_state[ 4] = %esi BoundTo %vr68 rreg_state[ 5] = %edi BoundTo %vr1 rreg_state[ 6] = %fake0 Free rreg_state[ 7] = %fake1 Free rreg_state[ 8] = %fake2 Free rreg_state[ 9] = %fake3 Free rreg_state[10] = %fake4 Free rreg_state[11] = %fake5 Free rreg_state[12] = %xmm0 Free rreg_state[13] = %xmm1 Free rreg_state[14] = %xmm2 Free rreg_state[15] = %xmm3 Free rreg_state[16] = %xmm4 Free rreg_state[17] = %xmm5 Free rreg_state[18] = %xmm6 Free rreg_state[19] = %xmm7 Free vreg_state[0 .. 77]: [1] -> 5 [8] -> 1 [68] -> 4 |