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From: <sv...@va...> - 2006-10-11 17:05:01
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Author: sewardj
Date: 2006-10-11 18:04:56 +0100 (Wed, 11 Oct 2006)
New Revision: 6209
Log:
Use 'ctr' rather than 'lr' as the base for indirect jumps. POWER4
likes that much better -- gives up to 15% speedup with --tool=3Dnone.
Modified:
branches/AIX5/coregrind/m_dispatch/dispatch-ppc32-aix5.S
Modified: branches/AIX5/coregrind/m_dispatch/dispatch-ppc32-aix5.S
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/AIX5/coregrind/m_dispatch/dispatch-ppc32-aix5.S 2006-10-11 1=
6:43:15 UTC (rev 6208)
+++ branches/AIX5/coregrind/m_dispatch/dispatch-ppc32-aix5.S 2006-10-11 1=
7:04:56 UTC (rev 6209)
@@ -296,10 +296,10 @@
/* Found a match. Call tce[1], which is 8 bytes along, since
each tce element is a 64-bit int. */
addi 8,5,8
- mtlr 8
+ mtctr 8
=20
/* run the translation */
- blrl
+ bctrl
=20
/* On return from guest code:
r3 holds destination (original) address.
@@ -362,10 +362,10 @@
/* Found a match. Call tce[1], which is 8 bytes along, since
each tce element is a 64-bit int. */
addi 8,5,8
- mtlr 8
+ mtctr 8
=20
/* run the translation */
- blrl
+ bctrl
=20
/* On return from guest code:
r3 holds destination (original) address.
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