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From: <sv...@va...> - 2006-09-11 16:59:29
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Author: sewardj
Date: 2006-09-11 17:59:25 +0100 (Mon, 11 Sep 2006)
New Revision: 1658
Log:
Merge r1656 (Support pextrw when the destination register is 64 bits
too. Fixes #133678.)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2006-09-11 16:54:29 U=
TC (rev 1657)
+++ branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2006-09-11 16:59:25 U=
TC (rev 1658)
@@ -9159,7 +9159,7 @@
/* ***--- this is an MMX class insn introduced in SSE1 ---*** */
/* 0F C5 =3D PEXTRW -- extract 16-bit field from mmx(E) and put=20
zero-extend of it in ireg(G). */
- if (haveNo66noF2noF3(pfx) && sz =3D=3D 4
+ if (haveNo66noF2noF3(pfx) && (sz =3D=3D 4 || sz =3D=3D 8)
&& insn[0] =3D=3D 0x0F && insn[1] =3D=3D 0xC5) {
modrm =3D insn[2];
if (epartIsReg(modrm)) {
@@ -9175,10 +9175,15 @@
case 3: assign(t5, mkexpr(t3)); break;
default: vassert(0);
}
- putIReg32(gregOfRexRM(pfx,modrm), unop(Iop_16Uto32, mkexpr(t5))=
);
+ if (sz =3D=3D 8)
+ putIReg64(gregOfRexRM(pfx,modrm), unop(Iop_16Uto64, mkexpr(t=
5)));
+ else
+ putIReg32(gregOfRexRM(pfx,modrm), unop(Iop_16Uto32, mkexpr(t=
5)));
DIP("pextrw $%d,%s,%s\n",
(Int)insn[3], nameMMXReg(eregLO3ofRM(modrm)),
- nameIReg32(gregOfRexRM(pfx,modrm)));
+ sz=3D=3D8 ? nameIReg64(gregOfRexRM(pfx,modrm)=
)
+ : nameIReg32(gregOfRexRM(pfx,modrm))
+ );
delta +=3D 4;
goto decode_success;
}=20
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